June 3, 2009 -- The digital downconverter (DDC) has become a cornerstone technology in communication systems. Similar to its analog receiver counterpart, the DDC provides the user with a means to tune and extract a frequency of interest from a broad radio spectrum.
Over the past few years, the functions associated with DDCs have seen a shift from being delivered in ASICs to operating as IP (intellectual property) in FPGAs.
For many applications, this implementation shift brings advantages such as design flexibility, higher precision processing, higher channel density, lower power and lower cost per channel. With the advent of each new higher performance FPGA family, these benefits continue to increase.
This article explores some of the key advantages of implementing DDC designs in FPGAs and describes some of the situations when ASICs can still offer the best solution.
By Richard Kuenzler and Robert Sgandurra. (Kuenzler is a Senior Design Engineer and Sgandurra is a Product Manager at Pentek, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Embedded website.
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