July 9, 2009 -- Participating in the consumer-electronics segment has many advantages. Despite that fact, design teams in this segment will encounter a drastically reduced time-to-market window. Consequently, FPGA (field-programmable-gate-array)-based designs have evolved as the first choice of many system architects. Meanwhile, the increasing requirement for multimedia in consumer products has made DSPs and streaming interfaces must-have components in many embedded products. Several FPGA vendors have developed FPGAs with DSP cores and streaming interfaces that are technologically sufficient and complex enough to handle these recent design requirements.
An FPGA interfacing with DSP cores and with high-speed-video data streaming through it is far from a simple system, however. This increased design complexity has added verification challenges and raised the specter of costly re-spins of the system board if you catch a critical error late in the design cycle. To put that ghost back to bed, you must carefully consider your approach to verification so that you can reduce the risk of costly re-spins.
The largest advantage of FPGA-based design verification is that, at the lowest level, the system has a predefined architecture, so you know the scope of necessary test scenarios at the beginning of the design. With this fact in mind, a verification team can build on the FPGA a verification environment that mimics the actual system architecture.
By Harshal Chhaya and Tarak Patel. (Chhaya is an ASIC engineer at eInfochips, Ltd. and Patel is an ASIC-verification engineer, also at eInfochips.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.
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