October 6, 2009 -- By their nature, FPGAs are power hungry devices with complex power delivery requirements and multiple voltage rails. A single chip commonly consumes multiple watts of power while operating from 1.8-V, 2.5-V and 3.3-V rails. Activating high speed on-chip SerDes can increase power consumption by several watts and complicate the power delivery strategy. When FPGA power consumption increases, performance requirements on sensitive analog and mixed-signal subsystems also increase. Chief among these are the clocking subsystems that provide low jitter timing references for the FPGA and other board-level components.
By Juan Conchas. (Conchas is the product marketing manager responsible for Silicon Laboratories, Inc.'s oscillator products.)
This brief introduction has been excerpted from the original copyrighted article.
Keywords: FPGAs, field programmable gate arrays, FPGA design, embedded system design, power supply design, clocks, clocking, Silicon Laboratories, EE Times Programmable Logic Designline,
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