| Stackable Architectures Diverge by EDN Magazine |
January 22, 2009 -- With recent additions to the official specification plus multiple customized variations to extract more performance, -like architectures continue to be prime candidates for rugged and space-constrained embedded designs. These ... read more |
| What’s In a System? by Synopsys, Inc. in Electronic Design Magazine |
January 21, 2009 -- Recently, there has been quite some discussion at conferences and in the blogosphere about system-level design, specifically around the term electronic system level (ESL). The buzz mostly centers around which technologies sho ... read more |
| Jasper, OneSpin Seek Broader Audience for Formal Verification Tools by EDN Magazine |
January 21, 2009 -- Formal property-checking tools—EDA tools that mathematically determine the truth of a set of properties for a given design in order to prove that a design will do what the designer intended—are reaching out for a wider market ... read more |
| The Value of High-Quality IP-XACT XML by NXP Semiconductors in Design & Reuse |
January 19, 2009 -- As the semiconductor industry increases take-up of IP-XACT standards to describe Intellectual Property (IP) this paper shares the experiences of NXP Semiconductors and Mentor Graphics, who have been using and developing this ... read more |
| Using FPGAs in Reliable Automotive System Design by Lattice Semiconductor Corp. in EE Times Automotive Designline |
January 15, 2009 -- The increased use of complex automotive electronics systems requires that they be designed for "ultra-reliability," because the failure of an automotive system could place the vehicle's passengers in a life-threatening situat ... read more |
| Filter Banks, Part 1: Principles and Design Techniques by Synopsys, Inc. in EE Times Signal Processing DesignLine |
January 15, 2009 -- Filter banks are part of a group of signal processing techniques that decompose signals into frequency subbands. This decomposition is useful because frequency domain processing (also called subband processing) has advantages ... read more |
| An Application Modeling and Hardware Description for Network-on-Chip Benchmarking by EE Times Embedded |
January 14, 2009 -- Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multicore/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far.
... read more |
| How to Transform Video SerDes From a Nightmare to a Dream by National Semiconductor Corp. in EE Times Programmable Logic Designline |
January 14, 2009 -- Many IC designers wake up at night with nightmares involving mixed-signal design. A classic example involves the design of high speed serializers and deserializers (SerDes). If a process is selected which will allow good perf ... read more |
| A Backplane Tutorial: RapidIO, PCIe and Ethernet by Tundra Semiconductor Corp. in EE Times Signal Processing DesignLine |
January 14, 2009 -- While there are many ways to connect components in embedded systems, the most prominent are the high speed serial standards of Ethernet, PCI Express, and RapidIO. All of these standards leverage similar Serializer/De-serializ ... read more |
| Architecting the OCP uVC Verification Component by Verilab, Ltd. in EE Times EDA Designline |
January 13, 2009 -- Architecting effective verification components for something as flexible as the Open Core Protocol requires a detailed understanding not only of the corresponding specification, but also the environments and methodology in wh ... read more |
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