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 Category: Special Topics: Timing Analysis & Closure: Friday, September 10, 2010
  Timing Analysis & Closure

Featured Articles

Accelerate Design Closure with Multi-Core Timing Analysis and Optimization

With the trend towards increasing IC design size and complexity showing no sign of slowing, the computing load required to complete projects on time is exploding. But, the growth in computing power is coming from multiple cores instead of higher clock speeds, which means IC implementation software must run efficiently on the latest multi-core hardware.

Although some implementation tasks (e.g., placement and routing) have been parallelized to a certain extent, parallelizing the very core of the physical design system — the timing analysis and optimization engines — is the smart way to improve runtimes and maintain tight design schedules. Scalable, parallel timing analysis and optimization capabilities can dramatically cut overall design time. “Parallel timing,” means that multiple timing calculations — which include extraction, delay and slew calculations, power, and signal integrity analysis — run concurrently via multiple threads on all available CPUs on all cores. This capability is not widely available in physical-implementation and timing-analysis tools, but can make the critical difference in time-to-closure.

Read the entire article by Mentor Graphics Corp. on SOCcentral.

Bridging SOC Architectures for Faster Timing Closure

The complexities of SOC timing closure are addressed in two fundamental ways today. The first is to continue to utilize new EDA tools in the design flow that improve simulation and analysis. A second way is to use architecture tools that help better predict behavior of key elements before the chip design begins, such as data flows and IP interoperability, to mitigate timing-closure risks before the chip is designed. Some companies today use both.

But given the levels of extreme complexity now on a single chip, and analyzing the directions that both the EDA and IP providers are taking to support each of the methodologies highlighted briefly above, is it time to revisit the basic architectural philosophies used for SOCs? And how does this help the timing-closure problem?

Read the entire article by ChipStart on SOCcentral.

Probabilistic Timing Analysis

Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, process variation has been one of the constant themes of IC designers as new process nodes are introduced. This article reviews the problem and proposes a "probabilistic" approach as a solution to analysis and management of variability.

Read the entire article by Library Technologies, Inc. on SOCcentral.

Designer's Mall

SOCcentral news items about Timing Analysis & Closure

EMA TimingDesigner 9.25 Automates Static Timing Analysis Process (9/1/2010)
Synopsys Galaxy Implementation Platform Used by TSMC for 28-nm Process (8/9/2010)
Silicon Laboratories Introduces Online Clock Tree Design Service (7/16/2010)
TSMC Adopts Azuro's Rubix for Embedded CPU Hardening (7/9/2010)
SiS Adopts Cadence Technologies for Advanced SOC Designs (6/30/2010)
Atrenta Announces SpyGlass-Physical for Early Implementation Analysis (6/17/2010)
Magma's Talus 1.1 Enables Faster Timing Closure for SOC Designs Incorporating High-Performance MIPS32 Processors (6/17/2010)
Mentor Graphics' Olympus-SoC Place-and-Route System Now Supported By X-FAB (6/17/2010)
PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances (6/17/2010)
Sigma Design Leverages Magma's Tekton to Accelerate Runtime and Reduce Hardware Costs for Static Timing Analysis (6/17/2010)
New Release of Azuro Rubix Delivers 15% Increase In Clock Frequency and Full Support for CPF 1.1 (6/14/2010)
Blue Pearl Software Introduces FPAT for Highest Level of Constraint Confidence (6/11/2010)
STARC Adopts Extreme GoldTime as Timing Tool in STARCAD-CEL (V4.0) Statistical IC Analysis Flow (6/11/2010)
XMOS Timing Analyzer Simplifies Development Cycles, Accurately Predicts Performance of Time-Critical Programs (5/18/2010)
Mentor Graphics Calibre InRoute Delivers True Manufacturing Sign-Off During Physical Design Closure (5/3/2010)
Nangate Announces Footprint Compatible IPO Module for Power Reduction and Faster Timing Closure (4/20/2010)
TSMC Expands Cadence Tool Support In Integrated Sign-Off Flow By Adding Synthesis, Place and Route, and RC Extraction (4/14/2010)
Magma Unveils Tekton Static Timing Analysis Solution with Fast Multi-Scenario Analysis on a Single CPU (3/11/2010)
Real Intent Releases Meridian CDC Version 3.0 (3/4/2010)
Discera Closes $11M Series D Financing (1/11/2010)
Synopsys Multicore Technology Speeds Timing Sign-Off by 2X (1/11/2010)
STARC Adopts Incentia TimeCraft for Static Timing and Signal Integrity Analysis Solutions (12/17/2009)
Altos Releases Variety MX for Statistical Memory Characterization (12/16/2009)
Atrenta's SpyGlass-CDC Solution Boosts IP Integration Efficiency for Fujitsu Kyushu Network Technologies (11/17/2009)
Wintegra Selects Magma's Talus As IC Implementation Platform for Low-Power, High-Performance 65-nm Chips (11/2/2009)

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Magazine & Journal articles on Timing Analysis & Closure

Web-Based IC Customization Revolutionizes Timing Circuits Electronic Products (7/1/2010)
Path-Specific Derating to Reduce Timing Pessimism EDN Magazine (6/25/2010)
Timing Closure in 45-nm ASICs Using Statistical Static Timing Analysis Design Methodology DAC Knowledge Center (6/17/2010)
Timing Closure On FPGAs Programmable Logic DesignLine (4/22/2010)
An Easy Way to Adopt Statistical Timing Analysis and Do Better Designs SOCcentral (1/21/2010)
Accelerate Design Closure with Multi-Core Timing Analysis and Optimization SOCcentral (11/2/2009)
Probabilistic Timing Analysis SOCcentral (10/31/2009)
Calculating Corner Independent Timing Closure Embedded Systems Design (embedded.com) (10/30/2009)
Board-Level Timing Analysis EDA Tech Forum (4/1/2009)
Establishing Timing Correlation Between Tools EDN Magazine (3/19/2009)
Statistical Static Timing Analysis: A Better Alternative EDA DesignLine (2/3/2009)
Golden Timing Signoff - Does It Correlate to Spice? SCDsource (12/7/2008)
Test Structures Make Designs Harder to Verify SOCcentral (10/28/2008)
FPGA Timing Closure: The Whack-a-Mole Game FPGA and Programmable Logic Journal (9/30/2008)
Clock Domain Crossing: Guidelines for Design and Verification Success EDA Tech Forum (9/1/2008)
Preserving the Intent of Timing Constraints EDA DesignLine (5/17/2008)
Validating False Path Timing Exceptions SCDsource (4/15/2008)
Statistical Timing Gets a Foothold in Leading-edge Designs EDN Magazine (3/24/2008)
Trip Points for IC Timing Analysis EDN Magazine (3/20/2008)
How to Achieve Timing-Closure in High-End FPGAs Programmable Logic DesignLine (1/23/2008)
Tame the Timing Margins in Your 65-nm Designs SOCcentral (1/3/2008)
Understanding Clock Domain Crossing Issues EDA DesignLine (12/24/2007)
Process Intelligent Modeling and Statistical STA improve DFM EDA DesignLine (9/11/2007)
Statistical Timing Analysis: Sign-off for a New Generation SOCcentral (7/19/2007)
Simultaneous Multi-Scenario Timing Optimization for High-Performance Digital IC Designs SOCcentral (7/12/2007)
Timing Constraints Generation Technology EDA DesignLine (5/17/2007)
Timing Is Everything in SOC Design EDN Magazine (1/4/2007)
Practical Applications of Statistical Static Timing Analysis EDA DesignLine (12/18/2006)
Cell Model Creation for Statistical Timing Analysis eeDesign (EE Times EDA News) (7/3/2006)
Evaluate IP Timing Constraints Before Use in SOC Designs SOCcentral (7/1/2006)
On-Chip Variation and Timing Closure EDN Magazine (6/22/2006)
Timing Analysis Rounds the Corner to Statistics Electronic Design Magazine (12/15/2005)
Clock Watching: Unraveling Complex Clocking FPGA and Programmable Logic Journal (3/29/2005)
The Impact of Timing Exceptions on FPGA Performance FPGA and Programmable Logic Journal (2/15/2005)
Reducing False Errors in Clock-Domain Crossing Analysis eeDesign (EE Times EDA News) (1/17/2005)
Analysis of Board Layout Helps Cure Jitter Problems EDN Magazine (8/5/2004)
FPGAs Go, Go, Go: Solving the FPGA Timing Closure Challenge for High-Speed Designs Chip Design Magazine (7/1/2004)
Tackling Multiple Clocks in SoCs Electronic Engineering Times (EE Times) (3/17/2004)
It Takes a Super Sleuth to Really Debug Clock-Timing Problems Electronic Design Magazine (2/16/2004)
Non-Linear Effects in Low-Power Sub-100nm Designs Electronic Engineering Times (EE Times) (1/15/2004)
Using RTL Floorplanning to Budget Nanometer Designs Electronic Engineering Times (EE Times) (1/15/2004)
"Best practices" Improve Hierarchical Design Constraints eeDesign (EE Times EDA News) (12/1/2003)
Skew Generation and Analysis in Timing-Critical Circuits EDN Magazine (11/13/2003)

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Tutorials, White Papers & Conference Papers on Timing Analysis & Closure

A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis (45.3) Design Automation Conference (DAC)
A General Framework for Accurate Statistical Timing Analysis Considering Correlations Design Automation Conference (DAC)
A General Framework for Spatial Correlation Modeling in VLSI Design (45.1) Design Automation Conference (DAC)
A Methodology to Improve Timing Yield in the Presence of Process Variations Design Automation Conference (DAC)
A Multi-Port Current Source Model for Multiple Input Switching Effects in CMOS Library Cells Design Automation Conference (DAC)
A New LP Based Incremental Timing Driven Placement for High Performance Designs Design Automation Conference (DAC)
A Timing-Driven Chip-Level Design Flow Design Automation Conference (DAC)
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis (9.3) Design Automation Conference (DAC)
An Approach to Placement-Coupled Logic Replication Design Automation Conference (DAC)
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs (52.2) Design Automation Conference (DAC)
An Efficient Retiming Algorithm under Setup and Hold Constraints Design Automation Conference (DAC)
Beyond DDR: Signal Integrity and Timing Analysis of Quad Band Memory (QBM) Systems Signal Integrity Software, Inc. (SiSoft)
Circuit Optimization Using Statistical Static Timing Analysis Design Automation Conference (DAC)
Clock Concurrent Optimization Azuro, Inc.
Clock Period Minimization with Minimum Delay Insertion (52.1) Design Automation Conference (DAC)
Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification Atrenta, Inc.
Comparative Analysis of Conventional and Statistical Design Techniques (14.1) Design Automation Conference (DAC)
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process (29.1) Design Automation Conference (DAC)
Correlation-Aware Statistical Timing Analysis with Non-Gaussian Delay Distributions Design Automation Conference (DAC)
Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model Design Automation Conference (DAC)
Design-Silicon Timing Correlation: A Data Mining Perspective (22.1) Design Automation Conference (DAC)
Efficient Timing Closure Without Timing Driven Placement and Routing Design Automation Conference (DAC)
Extraction of Statistical Timing Profiles Using Test Data (29.3) Design Automation Conference (DAC)
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction (14.2) Design Automation Conference (DAC)
Fast Statistical Timing Analysis with Arbitrary Delay Correlations Design Automation Conference (DAC)
First-Order Incremental Block-Based Statistical Timing Analysis Design Automation Conference (DAC)
Forest vs. Trees: Where's the Slack? Design Automation Conference (DAC)
Global Critical Path: A Tool for System-Level Timing Analysis (43.4) Design Automation Conference (DAC)
High-Speed Design Challenges for a 1.4GHz Network Processor Signal Integrity Software, Inc. (SiSoft)
Hold Time Validation on Silicon and the Relevance of Hazards in Timing Analysis Design Automation Conference (DAC)
How Accurately Can We Model Timing in A Placement Engine? Design Automation Conference (DAC)
Hybrid Timing Analysis Nassda Corp.
Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations (9.1) Design Automation Conference (DAC)
Meeting Timing Budgets for DDR Memory Interfaces Synopsys, Inc.
Nanometer Analysis Improves Timing Accuracy in Synthesis-Driven Flows Nassda Corp.
Noise-Aware Timing Analysis Cadence Design Systems, Inc.
Non-Linear Statistical Static Timing Analysis for NonGaussian Variation Sources (14.3) Design Automation Conference (DAC)
Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology Design Automation Conference (DAC)
On the Need for Statistical Timing Analysis Design Automation Conference (DAC)
Parameterized Block-Based Statistical Timing Analysis with Non-Gaussian Parameters and Nonlinear Delay Functions Design Automation Conference (DAC)
Piece-Wise Approximations of RLCK Circuit Responses using Moment Matching Design Automation Conference (DAC)
Rapid Estimation of Control Delay from High-Level Specifications Design Automation Conference (DAC)
Refined Statistical Static Timing Analysis Through Learning Spatial Delay Correlations Design Automation Conference (DAC)
Register Binding for Clock Period Minimization Design Automation Conference (DAC)
Robust Gate Sizing by Geometric Programming Design Automation Conference (DAC)
Silicon Speedpath Measurement and Feedback into EDA Flows (22.2) Design Automation Conference (DAC)
Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era Design Automation Conference (DAC)
STAC: Statistical Timing Analysis with Correlation Design Automation Conference (DAC)
Static Timing Analysis Using Backward Signal Propagation Design Automation Conference (DAC)
Statistical Framework for Technology-Model-Product Co-Design and Convergence (29.2) Design Automation Conference (DAC)
Statistical Gate Delay Model Considering Multiple Input Switching Design Automation Conference (DAC)
Statistical Logic Cell Delay Analysis Using a Current-Based Model Design Automation Conference (DAC)
Statistical On-Chip Communication Bus Synthesis and Voltage Scaling Under Timing Yield Constraint Design Automation Conference (DAC)
Statistical Static Timing Analysis: How Simple Can We Get? Design Automation Conference (DAC)
Statistical Timing Analysis Based on a Timing Yield Model Design Automation Conference (DAC)
Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining Design Automation Conference (DAC)
Statistical Timing Analysis with Correlated Non-Gaussian Parameters Using Independent Component Analysis Design Automation Conference (DAC)
Statistical Timing Based on Incomplete Probalistic Descriptions of Parameter Uncertainty Design Automation Conference (DAC)
Steiner Network Construction for Timing Critical Nets Design Automation Conference (DAC)
Test Generation in the Presence of Timing Exceptions and Constraints (38.4) Design Automation Conference (DAC)
The Case for the Precision Timed (PRET) Machine (15.2) Design Automation Conference (DAC)
Timing Closure for Low-FO4 Microprocessor Design Design Automation Conference (DAC)
Timing Closure through a Globally Synchronous Timing Partitioned Design Methodology Design Automation Conference (DAC)
Timing-Driven Steiner Trees are (Practically) Free Design Automation Conference (DAC)
Top-k Aggressors Sets in Delay Noise Analysis (10.3) Design Automation Conference (DAC)
Toward a Systematic-Variation Aware Timing Methodology Design Automation Conference (DAC)
Variational Delay Metrics for Interconnect Timing Analysis Design Automation Conference (DAC)
Worst-Case Circuit Delay Taking into Account Power Supply Variations Design Automation Conference (DAC)

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