Clock Domain Crossing Demystified
The increase in SOC designs is leading to the extensive use of asynchronous clock domains. The clock-domain-crossing (CDC) interfaces are required to follow strict design principles for reliable operation. Also, verification of proper CDC design is not possible using standard simulation and static timing-analysis (STA) techniques. As a result, CDC-verification tools have become essential in design flows. This article makes a fundamental observation that the inability to accomplish timing closure across the CDC interface is the root cause of the CDC problem. In addition, this article identifies practical considerations for effective CDC verification and recommends a hierarchical top-down, bottom-up methodology — with result inheritance and effective use of formal analysis — to minimize the manual engineering effort in CDC verification.
Read the entire article from Real Intent, Inc. on SOCcentral.
Accelerate Design Closure with Multicore Timing Analysis and Optimization
With the trend towards increasing IC design size and complexity showing no sign of slowing, the computing load required to complete projects on time is exploding. But, the growth in computing power is coming from multiple cores instead of higher clock speeds, which means IC implementation software must run efficiently on the latest multi-core hardware. Although some implementation tasks (e.g., placement and routing) have been parallelized to a certain extent, parallelizing the very core of the physical design system — the timing analysis and optimization engines — is the smart way to improve runtimes and maintain tight design schedules. Scalable, parallel timing analysis and optimization capabilities can dramatically cut overall design time.
Read the entire article from Mentor Graphics Corp. on SOCcentral.
Bridging SOC Architectures for Faster Timing Closure
The complexities of SOC timing closure are addressed in two fundamental ways today. The first is to continue to utilize new EDA tools in the design flow that improve simulation and analysis. A second way is to use architecture tools that help better predict behavior of key elements before the chip design begins, such as data flows and IP interoperability, to mitigate timing-closure risks before the chip is designed. Some companies today use both. But given the levels of extreme complexity now on a single chip, and analyzing the directions that both the EDA and IP providers are taking to support each of the methodologies highlighted briefly above, is it time to revisit the basic architectural philosophies used for SOCs? And how does this help the timing-closure problem?
Read the entire article from ChipStart on SOCcentral.
Probabilistic Timing Analysis
Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, process variation has been one of the constant themes of IC designers as new process nodes are introduced. This article reviews the problem and proposes a "probabilistic" approach as a solution to analysis and management of variability.
Read the entire article by Library Technologies, Inc. on SOCcentral.