Page loading . . .

 Category: Magazine & Journal Articles Online: Article Archive 2010: Saturday, October 22, 2016
Getting the Most Out of ASIC Prototyping with FPGAs  
Publication: EE Times Programmable Logic Designline
Contributor: Mentor Graphics Corp.
 Printer friendly
 E-Mail Item URL

February 7, 2010 -- Over the past 18 months, there has been a growing adoption of the use of FPGAs to prototype ASICs as part of an ASIC verification methodology. With the development costs for ASICs skyrocketing a typical 90-nm ASIC/SOC design tape-out today costs around $20M; a 90-nm mask set alone costs over $1M; and total development cost for a 45-nm SOC is expected to top $40M it is clear to see why avoiding a respin by prototyping with FPGAs is attractive.

Besides the increase in mask set cost, total development cost is also increasing due to the reduced probability of getting the design right the first time. As design complexity continues to increase, surveys have shown that only about a third of today's SOC designs are bug-free in first silicon, and nearly half of all re-spins are reported as being caused by functional logic error. As a result, verification managers are now exploring ways to strengthen their functional verification methodologies.

With increased complexity, another cost becomes a limiting factor to the effectiveness of verification simulation run-time and inaccuracy of stimulus models. Prototyping an ASIC design in FPGAs, while often yielding different performance, still results in the same logical functionality. Further, running a design at speed on an FPGA prototype with real stimulus allows for a far more exhaustive and realistic functional coverage as well as early integration with embedded software. Thus FPGA prototyping can be used effectively to supplement and extend existing functional verification methodologies.

By Darren Zacher. (Zacher is a Technical Marketing Engineer with Mentor Graphics Corp.'s Design Creation and Synthesis Division.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times Programmable Logic Designline website.

Read more about
Mentor Graphics Corp.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, ASIC prototyping,
596/30794 2/7/2007 4462 339
Designer's Mall

 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.596  0.28125