March 18, 2010 -- Digital signal processing is ubiquitous in modern electronic systems, from MP3 players to digital cameras to wireless handsets. One of the mainstays of a DSP designer’s tool box is the FIR (finite-impulse-response) filter. The longer the FIR filter—that is, the greater the number of taps—the better the filter’s response. This situation involves a trade-off, however, because more taps require increased logic requirements, increased computational complexity, increased power consumption, and a greater potential for saturation or overflow.
Designers can employ polyphase techniques to implement filters that provide comparable results and use less logic, requiring fewer computational resources, consuming less power, and having less potential for saturation and overflow. The resulting filters fit into today’s new class of smaller, mid-range FPGAs.
By Ron Warner. (Warner is Marketing Manager for SRAM FPGAs at Lattice Semiconductor Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.
