Publication: EE Times EDA Designline
Contributor: Satin IP Technologies
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March 17, 2010 -- Good EDA tools, even combined within well-automated flows, are not enough to produce quality designs, whatever those designs are for software, systems-on-chip (SOCs), integrated circuits (ICs), intellectual property (IP) or embedded systems.
Why is quality so difficult to achieve? Here are some of the things we are finding:
- Quality is often not defined operationally, making measurement and reporting onerous.
- Tools may be used incorrectly.
- Quality reporting is often informal, not objective, or comprised of too much information to be actionable.
- Worldwide teams and concurrent IP/ SoC/ software design produce burdensome quality monitoring overhead.
- Quality compromises tend to be made in order to meet tight schedules.
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How does one define quality measures so that they can be easily deployed and used? Every time there is a panel on quality, designers and design managers realize that a huge amount of question-and-answer time is spent on defining quality criteria. And that quality is not the same for every type of design or every company.
By Dr. Michel Tabusse. (Tabusse is CEO and co-founder of Satin IP Technologies.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
Read more about
Satin IP Technologies
on SOCcentral.com |
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, system-on-chip, SoC, EE Times EDA Designline, Satin IP Technologies,
| | 596/31013 3/17/2010 4133 195 | |
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