Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2010: Sunday, May 26, 2013
Power Management for Optimal Power Design  
Publication: EDN Magazine
Contributor: eSilicon Corp.
 Printer friendly
 E-Mail Item URL

May 27, 2010 -- Optimization of power consumption is one of the biggest challenges IC designers face today. Although power optimization has always been critical for battery-operated designs, the continued growth of system performance with each new generation of semiconductor technology, along with the increasing emphasis on "green" and "clean" technical applications, has made power optimization essential even for wall-powered designs. Effective power management involves selection of the right technology, the use of optimized libraries and IP (intellectual property), and design methodology. It also means optimizing both active dynamic power and static leakage power. This article examines the various approaches to effective power management.

Prasad Subramaniam, Ph.D. (Subramaniam is Vice President of Design Technology at eSilicon Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EDN Magazine website.

Read more about
eSilicon Corp.
on SOCcentral.com

Keywords: ASICs, ASIC design, IP, intellectual property, cores,EDA, EDA tools, electronic design automation,low power design, low-power design, power analysis,power optimization, EDN Magazine, eSilicon,
596/31496 5/27/2010 2818 212


Designer's Mall
0.1884766



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.596  0.2177734