June 17, 2010 -- In today's semiconductor designs, lower power consumption is mandatory for mobile and handheld applications for longer battery life and even networking or storage devices for low carbon footprint requirements. Clock power consumes 60% to 70% of total chip power and is expected to significantly increase in the next generation of designs at 45nm and below. This is due to the fact that power is directly proportional to voltage and the frequency of the clock. Hence, reducing clock power is very important.

Clock gating is a key power-reduction technique used by many designers and is typically implemented by gate-level power synthesis tools. In this article, we will discuss the use of clock gating techniques with design examples for achieving lower power and also highlight the impact of clock gating on different areas of the design process like metastability with clock domain crossings and testability. The article also details the do's and don'ts of clock gating to avoid chip failures and unnecessary power dissipation.

By Narayana Koduri and Kiran Vittal. (Koduri and Vittal are with Atrenta, Inc.)