June 15, 2010 -- Clock gating is a well-understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires that the designers add a small amount of logic to their RTL code to disable or deselect unnecessarily active sequential elements registers.
Despite the obvious value of reduced dynamic power afforded by this method, the designer faces significant challenges when attempting to perform these optimizations manually. Truly reducing activity in the design requires intimate knowledge of the design itself and typically requires numerous changes to the RTL.
Most ASIC and FPGA designs today comprise some combination of new, legacy, and third-party IP circuit designs, but typically only the new designs are candidates for clock-gating optimizations. Designers rarely, if ever, attempt these optimizations on legacy and IP design. They usually do not have sufficient depth of knowledge about the design and operation of the legacy RTL code, and it requires too much time to manually develop meaningful clock-gating optimizations.
Applying clock-gating optimizations usually requires the addition of more tools and more steps to the design flow and can precipitate the creation of an intricate set of new clocks requiring complex timing analyses (as is often the case for ASIC optimization). Unless the gains in power efficiency are sufficient and essential to the success of the design, the additional complexity and time can be prohibitive and add risk.
By Frederic Rivoallon. (Rivoallon is Synthesis Methodology Manager at Xilinx, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Programmable Logic Designline website.
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