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 Category: Magazine & Journal Articles Online: Article Archive 2010: Thursday, May 23, 2013
How to Achieve 1 Trillion Floating-Point Operations-per-Second In an FPGA  
Publication: EE Times Programmable Logic Designline
Contributor: Altera Corp.
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September 14, 2010 -- Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

By Michael Parker. (Parker is Senior DSP Technical Marketing Manager responsible for Altera Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

Read more about
Altera Corp.
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Keywords: FPGAs, field programmable gate arrays, FPGA design, DSP functions, Altera, EE Times Programmable Logic Designline,
596/32152 9/14/2010 1047 201


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