September 16, 2010 -- SerDes (serializers/deserializers) are devices that can take wide bit-width, single-ended signal buses and compress them to a few, typically one, differential signal that switches at a much higher frequency rate than the wide single-ended data bus. SerDes enable the movement of a large amount of data point-to-point while reducing the complexity, cost, power, and board space usage associated with having to implement wide parallel data buses. SerDes usage becomes especially beneficial as the frequency rate of parallel data buses moves beyond 500 MHz (1000 Mbps).
At these higher-frequency rates, the problems associated with wide parallel buses are further exacerbated. A faster-switching parallel bus consumes more power and is much more difficult to route, given that timing tolerances are reduced.
For example, system designers often have a very difficult time maintaining comparable skew between the individual. parallel-signal lines. Large skew mismatches can lead to system-timing issues at the receiver as many systems need to clock in the parallel data as a group of aligned bits.
Many other problems arise for parallel data-bus implementations as frequency and transmission distance increase. Issues such as signal integrity, power usage, and timing can all have a significant impact on a design. In today's compact systems, simply using many slower parallel channels to transport more data is not an acceptable answer as board space is often limited. In many applications, a SerDes can provide a very good solution for moving a large amount of data point-to-point within systems, between systems, or even between systems in two different locations.
By Atul Patel. (Patel is New Business Development Manager for Gigabit SerDes products within the Communication Interface Products Group at Texas Instruments, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Planet Analog website.
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