October 28, 2010 -- One of the major barriers for semiconductor IP commercialization is to provide evidence for an IP's quality. A common approach by IP vendors is to prove the quality of their IP in a test chip. Usually the die contains the IP block separated from the system-on-chip (SOC). It is, though, uncertain how the block will function in ASSP and ASIC products, potentially damaging its perceived commercial value.
The current model of an IP company is usually based on a single IP product, providing a specific functionality, independent of the market and the application in which the targeted product for that IP is going to be used. This model in fact, is the main criteria determining the value and the quality of an IP.
Being totally agnostic to the rest of the chip, the application and market in which the IP is targeted for integration, diffuse any attempt to prove the quality and determine the value of the IP; which elevates the risk of using the IP for a certain device.
In Rosetta's methodology, the IP core is a block within a subsystem, integrated to enable the subsystem functionality and targeted for a specific market and application. By analyzing the specific requirements of the market and application, and by providing an IP package targeted at those requirements, we solve and mitigate the IP quality risk. Rosetta's methodology turns the IP block into a solution rather than a standalone block within the SOC.
This article describes the making of such an analysis, as well as a comparison between different IP blocks, stressing the commercial and technical differences between standalone blocks and application-specific IPs.
By Gerardo Nahum and Omri Raisman. (Gerardo Nahum and Omri Raisman are co-founders of Rosetta IP.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
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