November 18, 2010 -- Among various pre-silicon solutions, software-simulation platforms have always been the preferred environment due to early availability, ease of use, ease of access, lower cost as compared to FPGAs and higher speeds as compared to RTL simulators. At Texas instruments we leverage pre-silicon software platforms for software benchmarking, architecture analysis, SOC validation as well as software development to meet time-to-market goals. These software platforms are mostly bit-accurate, functionally accurate and even timing-approximate, in some cases, compared to their hardware counterparts.
These system-on-chip platform simulators are developed by integrating C/C++-based IP models that are essentially the software variants of the hardware IP blocks like CPUs, caches, interrupt controllers, DMA's, hardware accelerators, external memory interface and serial peripherals. The functional and cycle accuracy of the software platform integration as well as that of individual IP models is critical for usefulness of these software platforms at an early stage of any chip program.
Though ESL bodies and EDA tool vendors are trying to bridge the gaps by defining and leveraging standards for bus infrastructure and modeling like SystemC, SCV and TLM2, the current verification approach for a C/C++ IP model remains weak.
This article discusses a "standalone" verification framework that is independent of any specific flow but still allows reuse of design verification and application tests to measure and debug the cycle accuracy as well as functional accuracy of an IP. As an additional benefit, the component validation speed and turn-around time to fix bugs is improved since the full system simulation environment is not required.
By Amit Nene and Swaminathan Ramachandran. Nene and Ramachandran are both with Texas Instruments, Inc.
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
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