|Publication: EDN Magazine|
Contributor: Silicon Creations
December 2, 2010 -- PLLs (phase-locked loops) are common analog circuits in SOCs (systems-on-chip). Almost all SOCs with a clock rate greater than 30MHz use a PLL for frequency synthesis. However, a "one-size-fits-all" PLL does not exist. The devices have a range of frequency, power, area, performance, and functions. PLLs implemented in 100-nm or smaller processes typically range in frequency from 10MHz to 10GHz. Their power spans from less than 1mW to more than 100mW. Their size can vary from 0.04 to 2mm˛, and their performance, which you typically measure as output jitter, ranges from more than 100fs to more than 10ps.
The wide range of specifications is the result of the wide range of end uses. Some uses include digital-logic or processor clocking, analog-front-end ADC/DAC clocking, serial-link communication, and RF synthesis. This article focuses on frequency-multiplication PLLs, but many other types exist.
Jeff Galloway and Randy Caplan. (Galloway is a co-founder of and Caplan is co-founder and Vice President of Engineering at Silicon Creations.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.
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|Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, PLLs, phase locked loops, system-on-chip, SoC, EDN Magazine, Silicon Creations, |
|596/32784 12/2/2010 980 239|