December 15, 2010 -- Since its debut in 2004, the current generation of high-level synthesis (HLS) tools has made tremendous progress in terms of both quality of results (QoR) and wider applicability. The success of this technology cannot be denied: HLS is here to stay. However, as in other arenas of electronic design automation, a language war threatens to divide the user community, pitting C/C++ against SystemC. While some rallied around a more abstract form of modeling in pure untimed C++, others argued for more detailed models; such as the explicit timing, structure, and parallelism of SystemC.
These two standard languages do serve different design needs; yet for this very reason they complement each other to great advantage in a mixed-language HLS flow. For example, while the complex algorithms of next-generation broadband modem ASICs are most effectively expressed in pure C++, the intricate control logic found in other parts of the same device benefit from SystemC cycle-accurate models.
Today, a new era of peace has already begun with the introduction of dual-language HLS tools. Designers can now express complex interface protocols using a timed SystemC source while keeping the rest of the design functionality in pure untimed ANSI C++. And they can express structure and hierarchy either by using SystemC modules or by inferring them from natural C++ boundaries. Now that HLS tools can deliver full-chip synthesis, both pure C++ and SystemC are needed to provide the most efficient and productive way to handle all the various parts of the system.
By Thomas Bollaert and Mike Fingeroff. (Bollaert is product marketing manager for high-level synthesis at Mentor Graphics and Fingeroff is a technical marketing engineer for the Catapult C product line at Mentor Graphics.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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