Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2010: Monday, December 22, 2014
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (303 Entries)
Architecture-Oriented C Optimizations  by CEVA, Inc. in Design & Reuse

January 14, 2010 -- Know your hardware! That's what it's all about. Using programming guidelines derived from the processor's architecture can dramatically improve performance of C applications. In some cases, it can even make the difference bet ... read more

Low-power LDPC Decoder Created Using High-Level Synthesis  by Synfora, Inc. in EE Times EDA Designline

January 13, 2010 -- With the popularity of mobile wireless devices soaring, the wireless communication market continues to see rapid growth. However, with this growth comes a significant challenge. Many applications, such as digital video, need ... read more

Using An FPGA to Tame the Power Beast In Consumer Handheld MPUs  by eInfochips, Ltd. in EE Times Programmable Logic Designline

January 13, 2010 -- The consumer handheld market is growing by leaps and bounds. With more processing power and increased support for more applications, portable products are cross-pollinating with traditional computing systems even as the produ ... read more

Deterministic Dynamic Memory Allocation and Fragmentation in C and C++  by Mentor Graphics Corp. in EE Times Embedded

January 11, 2010 -- In C and C++, it can be very convenient to allocate and de-allocate blocks of memory as and when needed. This is certainly standard practice in both languages and almost unavoidable in C++. However, the handling of such dynam ... read more

A Real Solution for Mixed Signal SOC Verification  by Intrinsix Corp. in EE Times EDA Designline

January 7, 2010 -- As more complex, mixed signal system-on-chip (SoC) designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed-signal verification presents a uni ... read more

Under the Lid: Analog Test Is Suddenly the Critical Ingredient  by EDN Magazine

January 7, 2010 -- ATPG (automatic-test-pattern generation), BIST (built-in self-test), and structural-test techniques have kept digital-test costs nearly constant during the explosion in digital complexity. Without these tools, however, as anal ... read more

Power Supply Design Considerations for Modern FPGAs  by National Semiconductor Corp. in EE Times Programmable Logic Designline

January 6, 2010 -- Today's FPGAs tend to operate at lower voltages and higher currents than their predecessors. Consequently, power supply requirements may be more demanding, requiring special attention to features deemed less important in past ... read more

Determine IC Transient Thermal Behavior to Prevent Overheating  by Maxim Integrated Products, Inc. in EDN Magazine

January 6, 2010 -- This article presents a method for predicting thermal behavior in integrated circuits. After characterizing thermal behavior, we formulate a mathematical model that simulates transient temperatures within the chip. We introduc ... read more

Using OVM to Reuse Vital Verification Knowledge  by Mentor Graphics Corp. in EE Times EDA Designline

January 5, 2010 -- Reuse of legacy directed test environments is common practice but, with each generation of reuse, the number of tests grows and with it the overhead of maintaining the environment across multiple projects. Another concern lies ... read more

A New Approach to Improving System Performance  by EE Times Embedded

January 5, 2010 -- Speed is a key element in most every electronic design. Though hardware usually gets first consideration when design teams look for ways to improve speed, that's not usually the most effective path. It's fairly straightforward ... read more




 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Executive
Viewpoint

Verification Contortions


Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Executive
Viewpoint

Deep Semantic and Formal Analysis


Dr. Pranav Ashar
CTO, Real Intent

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts
Newsletters



About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.596  0.359375