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 Category: Magazine & Journal Articles Online: Article Archive 2011: Monday, May 20, 2013
Major Changes Expected for Physical Verification Tools as Designs Move into 28nm and Below  
Publication: Electronic Engineering Times (EE Times)
Contributor: POLYTEDA Software Corp.
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March 8, 2011 -- As the semiconductor industry is charging forward with its process technologies, the electronic design automation (EDA) industry is trying to keep in step with the process advances. While EDA tools have done a reasonably good job of keeping up, the recent trends in process technologies have created new needs, for instance, the need to move from a compute farm to a compute "ranch" for physical verification. And still run-times take several hours, or even days. Most of these tools were architected using algorithms and concepts that were developed in the 1990s (some even in the 1980s) and are unable to meet the runtime and scalability needs for the advanced process technologies, today and tomorrow.

By Vlad Marchuk. (Marchuk is CTO and founder, POLYTEDA Software Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Electronic Engineering Times (EE Times) website.

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POLYTEDA Software Corp.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, physical verification, POLYTEDA Software, Electronic Engineering Times (EE Times)
599/33398 3/8/2011 1128 174


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