Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2011: Thursday, May 23, 2013
Hardware/Software Integration: Closing the Gap  
Publication: EE Times EDA Designline
Contributor: InPA Systems, Inc.
 Printer friendly
 E-Mail Item URL

March 13, 2011 -- In recent years, system integration associated with system-on-chip (SOC) design has grown at a rapid rate and continues to drive the semiconductor design market. Although this growth has been beneficial for the design community, the sophisticated and complex manufacturing requirements of next-generation devices have increased the cost of ASIC and ASSP development.

Product implementation of complex, low-power designs requires early integration of various hardware features with corresponding firmware onto one silicon device. The reduced life-span of current products have condensed SOC development cycles and have made the SOC verification and in-system validation process an arduous task. The bulk of time spent during the product development cycle of SOCs is often in hardware/ software integration and has brought in-system validation to the forefront of this extensive process.

By Tom Huang and Pete Mar. (Huang is CTO/ founder, InPA Systems, Inc. and Mar is a Senior Field Applications Engineer at InPA Systems.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
InPA Systems, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, hardware/software integration, InPA Systems, EE Times EDA Designline, system-on-chip, SoC,
599/33458 3/13/2011 1170 171


Designer's Mall
0.15625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.599  0.234375