|Publication: Chip Design Magazine|
Contributor: Altos Design Automation, Inc.
April 1, 2011 -- What keeps SOC designers up at night? It's the fact that they are now integrating many third-party IP blocks into their next-generation 2011 chips yet they have little or no control on how these subcomponents were created, verified and modeled. Of course, for the most part these third-party IP blocks are both welcome, and a design lifeline for SOC designers faced with aggressive deadlines and ever increasing complexity. However, the integration of IP blocks is not a simple task, especially with external IP blocks. The common practice of guard-banding as a fail safe is no longer viable as it results in overdesigned, lower performing, energy inefficient chips that miss their target markets.
What can we do about this discontinuity in chip design?
Even though there are currently over 200 IP design companies, (some of which have been hugely successful), users don't quite trust the technical veracity of the IP. This isn't just "trust” in the IP provider (the company or the people creating the IP) but infallible "trust” that the IP will work for their specific applications.
By Jim McCanny. McCanny is CEO of Altos Design Automation, Inc.
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Chip Design Magazine website.
Read more about
Altos Design Automation, Inc.
|Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, IP, intellectual property, cores, Altos Design Automation, Chip Design Magazine, |
|599/33674 4/1/2011 1803 112|