Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2011: Wednesday, May 22, 2013
Platforms Continuum for System Realization  
Publication: Embedded Computing Design
Contributor: Cadence Design Systems, Inc.
 Printer friendly
 E-Mail Item URL

May 5, 2011 -- The electronics industry is moving from being hardware-defined to being system-defined, while electronic products become increasingly application-driven. As a result, product differentiation has shifted to system (software-based) content, while hardware platforms and their development processes become more and more commoditized. Seizing new opportunities in this emerging segment requires expanding upon the foundations of the electronics industry. The needs of system developers must be addressed, and the responses to those needs must be integrated into a single solution.
The potential risks involved with schedule delays and product quality have become vast. Time-to-market pressures and the trend toward software-defined product functionality make the traditional sequential process, where system-on-chip (SOC) development is followed by board and device development and then by software development, obsolete. Meeting functionality, power, and performance as system bring-up occurs has become the most challenging task. System bring-up consumes one-third to one-half of the overall development cycle for many OEM companies, with product quality and predictability becoming the second and third priorities. System bring-up is a top OEM executive concern, as it can make or break the profitability of their products.

By Ran Avnium. (Avnium is with Cadence Design Systems, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Embedded Computing Design website.

Read more about
Cadence Design Systems, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, electronic system level design, electronic system-level design, ESL, Embedded Computing Design, Cadence Design Systems,
599/33798 5/5/2011 1066 168


Designer's Mall
0.3125



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.599  0.421875