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 Category: Magazine & Journal Articles Online: Article Archive 2011: Wednesday, June 19, 2013
Performance Evaluation of Inter-Processor Communication Mechanisms on the Multicore Processors Using a Reconfigurable Device  
Publication: Design & Reuse
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August 4, 2011 -- Recently, multi-core processors have been featured in embedded field. Especially, with regard to reconfigurable devices, several system constructions can be implemented easily. The real-time OS (RTOS) for a multicore processor has many limitations for system constructions on the reconfigurable devices. Therefore, it is very important to verify that the system construction satisfies the limitations for RTOS and that the primitive system calls operate properly. In addition, when these devices are used in the system development such as task design, the consumption of hardware/software resources, and the performance evaluation of primitive system calls on the reconfigurable devices are very important.

In this article, we propose several inter-processor communication mechanisms for two multicore processors on an FPGA as the primitive operations for the system tasks and evaluate them. We adopted NIOS II processor as the embedded processors and the TOPPERS/ FMP kernel as the operating system for multicore processor.

By Yasue Nagumo, Junji Kitamichi and Kenichi Kuroda. (The authors are with the University of Aizu, Aizuwakamatu JAPAN.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Design & Reuse website.

Keywords: FPGAs, field programmable gate arrays, FPGA design, embedded system design, embedded systems, real-time operating systems, RTOS, microprocessors, MPUs, multicore processors, multi-core processors, Design & Reuse,
599/34404 8/4/2011 685 135
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