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 Category: Magazine & Journal Articles Online: Article Archive 2011: Tuesday, June 18, 2013
25-28Gbps SerDes Design and Implementation Challenges  
Publication: Chip Estimate Corp.
Contributor: MoSys, Inc.
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October 4, 2011 -- As data-rates increase, more and more companies are relying on the expertise of 3rd party IP vendors, such as MoSys, who make SerDes their lifeblood and can leverage the cost of developing an IP across multiple customers. MoSys is an industry leader in multi-protocol IP designs with offerings spanning data-rates from 1-Gbps to 28-Gbps, including designs which push the limits of wire-bond packaging higher. This article focuses on SerDes architecture, modeling, and important aspects of implementing 25/28-Gbps standards.

By Dr. Claude Gauthier. (Gauthier joined MoSys in 2007 and is responsible for the Advanced SerDes IP Development group which designs multi-protocol IP.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Chip Estimate Corp. website.

Read more about
MoSys, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, serializer/deserializer, SerDes, Chip Estimate, MoSys,
599/34827 10/4/2011 2318 116
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