| When It Comes to Runtime Chatter, Less Is Best by Mentor Graphics Corp. in XCell Journal Online |
March 22, 2011 -- The end goal of a testbench is to show that your design achieves its purpose without having any bugs. Getting to that point, however, takes work. You will have to find, diagnose and fix bugs, in both the testbench and the desig ... read more |
| Time-Domain Simulations of High-speed Links with X Parameters by EE Times RF & Microwave Designline |
March 21, 2011 -- The design of reliable high-speed links is a challenging task because of the stringent electrical specifications for those systems. Modeling and simulation tools that can help predict the performance and optimize the design of ... read more |
| What Makes an Optimal SOC Verification Strategy by EE Times EDA Designline |
March 21, 2011 -- During the last decade, connected devices resulting from cross pollination of Internet and mobile phone technologies dominated the electronics world. Personalized products and services have penetrated our society so much that i ... read more |
| System Awareness Improves SOC Power Management by AppliedMicro Corp. (AMCC) in EE Times Power Management Designline |
March 18, 2011 -- Reducing the power consumption of SOCs (system on chip) has become increasingly important in electronic system designs, even when there are no batteries involved. Improvements in device-level methods are one step in the enhance ... read more |
| Complete IC Simulation Requires a Full Toolbox of Hardware and Software by EDN Magazine |
March 17, 2011 -- Discovering a design error after you send your average chip to manufacturing can be costly and embarrassing, not to mention hazardous to your career. To avoid missing design errors, you and your team must as thoroughly as possi ... read more |
| System Design Using NAND Flash Memory by Micron Technology, Inc. in EE Times Memory Designline |
March 17, 2011 -- NAND Flash error correcting code (ECC) has been on the rise since NAND was first introduced. Although it's not a new issue, the ECC required to support newer multilevel (MLC) and three-bit-per-cell technologies is becoming incr ... read more |
| Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment by Evatronix SA in Design & Reuse |
March 17, 2011 -- The article describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM mod ... read more |
| A 55-nm Ultra-Low-Leakage SRAM Compiler with Optimized Power-Gating Design by Design & Reuse |
March 17, 2011 -- In this article, an optimized power-gating design on a 55-nm static random access memory (SRAM) compiler is presented. Two low-leakage modes: retention and sleep mode are discussed. The arrangement of power gating (PG) MOS is e ... read more |
| Surpassing the Bandwidth Limitations of Cache-Based Processing Architectures by EDN Magazine |
March 17, 2011 -- The amount of network traffic in today’s wired and wireless infrastructures continues to rise at dramatic rates to keep up with the demand for IP (Internet Protocol)-based voice, video, and data services and applications. Cisco ... read more |
| Treat ICs, Packages, and PCBs as System Designs by Electronic Design Magazine |
March 16, 2011 -- The myriad challenges of designing a chip on its own range from functional correctness to power and signal integrity and manufacturability. Chips do not exist in isolation. Instead, they must be integrated into a system context ... read more |
|
