| Electrostatic Discharge Testing Standards: Understanding and Comparing the Differences by Texas Instruments, Inc. (TI) in EE Times Planet Analog |
September 12, 2011 -- Electrostatic discharge (ESD) is defined as "the sudden and momentary electric current that flows between two objects at different electrical potentials." ESD causes equipment failure and network downtime, thus, causing pro ... read more |
| Cell-Aware Fault Models for IC Production Test Outperform Gate-Exhaustive Fault Models by Mentor Graphics Corp. in Electronic Engineering Journal |
September 8, 2011 -- Physical defects within ICs, such as shorts and opens, can occur during manufacturing at any step along the fabrication process because of the complexity of modern CMOS technology nodes. The conventional approach to test for ... read more |
| Chip-and-Package Co-Design Relieves Pressure on Complex Designs by Texas Instruments, Inc. (TI) in EDN Magazine |
September 8, 2011 -- The vise is closing down on design departments. Manufacturers want more capabilities in their products than ever before. It's imperative for manufacturers to remain competitive. Marketing, meanwhile, wants to cram that added ... read more |
| Verifying Certified Software: Making the Most of the Tools You Have by Green Hills Software, Inc. in EE Times Embedded |
September 6, 2011 -- Software projects pursuing a DO-178B Level A certification will often follow a traditional software lifecycle model. Modern implementations of these processes have two key components in common: First, they all involve an ite ... read more |
| The Benefits of FireWire on PCI Express by LSI Corp. in EE Times MCU Designline |
September 5, 2011 -- PCI Express includes many features that can be taken advantage of by high-speed protocols such as IEEE 1394b (FireWire) to provide benefits to the consumer: increased bandwidth and more efficient performance, reduced board f ... read more |
| The Key to Realizing Full Multicore Design Functionality by Texas Instruments, Inc. (TI) in EE Times Embedded |
September 2, 2011 -- Continued evolution of the functionality required to meet performance and cost targets makes this a great time for designers to undertake a deep exploration of the architectural underpinnings of multicore solutions they are ... read more |
| Breaking the Language Barriers: Using Coverage Driven Verification to Improve the Quality of IP by Mentor Graphics Corp. in Design & Reuse |
September 1, 2011 -- Technology advances allows for the creation of larger and more complex designs. This poses new challenges, including efforts to balance verification completeness with minimization of overall verification effort and cycle tim ... read more |
| Transitioning to Multicore Processing by Freescale Semiconductor, Inc. in EE Times Embedded |
August 31, 2011 -- The transition to multicore processing requires changing the software programming model, scheduling, partitioning, and optimization strategies. Software often requires modifications to divide the workload among cores and accel ... read more |
| 3D ICs Without TSVs? by EDN Magazine |
August 30, 2011 -- Two assumptions have become accepted truths in SoC planning: first, that the way forward involves 3DICs; and second, that 3DICs require through-silicon vias (TSVs.) One result has been a tremendous focus on the challenges of T ... read more |
| Programmable Oscillators Enhance FPGA Applications by SiTime Corp. in EE Times Programmable Logic Designline |
August 29, 2011 -- Today's complex FPGAs contain large arrays of functional blocks for implementing a wide variety of circuits and systems. Often, these FPGAs use multiple clocks to drive different blocks, typically generating them using a combi ... read more |
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