May 4, 2011 -- ARM has announced the release of its fourth-generation memory interface solution, comprising the Dynamic Memory Controller (DMC-400) and an ARM Artisan DDR PHY hard macro, targeting high-performance, low latency SOC applications. ARM's memory interface solution is specifically designed to augment the performance of ARM Cortex-A series processors, including the Cortex-A9 and Cortex-A15 MPCore processors, enabling the development of high-bandwidth, high-efficiency multicore systems. The controller and the PHY (40nm) have already been licensed by a number of major customers including LG Electronics.

The ARM CoreLink DMC-400 implements advanced memory scheduling to deliver an industry-leading memory utilization efficiency in excess of 90% across multiple memory channels, interfacing through a DFI 2.1-compliant PHY to DDR2, DDR3 or LPDDR2 DRAM products. The CoreLink DMC-400 is the first memory controller designed to integrate with the 4 ACE or AMBA3 AXI3 interfaces, sharing a system-wide QoS that guarantees bandwidth and latency contracts from processor though to external memory.

The Artisan PHY hard macro is a high-speed physical interface covering a broad range of DDR (double-data rate) applications ranging from high-speed mission critical to low-power memory sub-systems. This silicon-proven (40-nm) solution has been optimized for high data bandwidth, lowest power and enhanced signal-integrity features to enable support for a wide range of applications from high-end graphics, high-speed communications to low-power handheld. Incorporating a multi-row pad architecture for the smallest footprint, the PHY supports flip-chip and wirebond package options at 40nm.