June 28, 2011 -- SynaptiCAD, Inc. has updated BugHunter, it's graphical test bench generator and HDL debugger, to add support for SystemC simulations. Standalone SystemC and mixed SystemC/ Verilog/ VHDL simulations can be compiled and debugged under the BugHunter GUI.

The new environment simplifies compiling regular C++ applications in conjunction with an HDL simulation as well (for example, to compile a PLI-based application loaded by a Verilog simulator). The new version also supports syntax color-coded tabbed editor windows for C++ files and loading VCD files generated by SystemC simulations. VCD files can also be saved in SynaptiCAD's compressed btim format for faster loading and editing.

Detect simulation race conditions

BugHunter lets users quickly swap between simulators from different EDA vendors, enabling detection of race conditions that are often missed when testing is performed with only one simulator. In addition to supporting SynaptiCAD's own simulator, Verilogger Extreme (now offered free of charge for a 6-month period), it also supports Mentor Graphics ModelSim, Cadence NCSim, and Aldec ActiveHDL. The latest version of VeriLogger Extreme also supports new options for changing the default ordering of processes, enabling detection of races without requiring access to an additional third party simulator.

Quickly analyze signal cause-effect relationships

BugHunter has also updated its cause-effect dependency windows that show relationships between signals and process statements in a Verilog simulation and let users quickly navigate through their designs to find a root cause for a value change on a wire or register. The updated cause-effect windows display changes in signal values since the last simulation step color-coded red to indicate the dependent signals that could be responsible for a value change. Signal and register values can also be changed from the cause-effect windows now.

Pricing and Availability