September 19, 2011 -- Cadence Design Systems, Inc. today announced that Fujitsu Semiconductor, Ltd. has adopted Cadence sign-off design-for-manufacturing (DFM) technologies for its 28-nanometer ASIC and system-on-chip (SOC) mixed-signal designs. Deploying the Cadence DFM offerings helps Fujitsu Semiconductor engineers ensure high yield, predictability, and a faster path to Silicon Realization for next-generation chips. The Cadence end-to-end digital and analog flows for Silicon Realization deliver DFM in-design technology within the Virtuoso custom/ analog and Encounter digital flows.

"After an extensive evaluation of all vendors in the market, we selected the complete Cadence DFM set of technologies for our most advanced ASIC and SOC designs," said Hiroshi Ikeda, Director of the System LSI Technology and Design Platform Development Department at . "The production-proven DFM technology gives us confidence in our ability to manage the complexity of advanced 28-nanometer effects in the fastest turn-around time, with the highest quality of silicon. Also, the seamless integration into the Cadence Virtuoso and Encounter flows makes it very straight-forward for our design teams to adopt and fully leverage in their day-to-day work."

Following comprehensive benchmarking, Fujitsu Semiconductor selected the Cadence Litho Physical Analyzer, Cadence CMP Predictor and Cadence Litho Electrical Analyzer for 28-nm in-design physical sign-off and variability optimization for its ASIC and SOC designs.

The Cadence Litho Physical Analyzer leverages proprietary, foundational algorithms to provide near-linear scalability, providing fast silicon convergence. The Cadence CMP Predictor allows Fujitsu Semiconductor engineers to detect topography variations of their manufacturing process early on via extensive simulations. Fujitsu Semiconductor design teams use the Cadence Litho Electrical Analyzer to identify and optimize their libraries for layout-dependent effect variability early on, therefore ensuring that their design meets their planned performance metrics.