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 Category: News: News Archive 2011: Saturday, October 22, 2016
Lattice Semiconductor Introduces Next-Generation LatticeECP4 Family  
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November 28, 2011 -- Lattice Semiconductor Corp. has announced of the next-generation LatticeECP4 FPGA family, with 6-Gbps SerDes in low-cost wire-bond packages, powerful DSP Blocks and hard IP-based Communication Engines for cost- and power-sensitive wireless, wireline, video and computing markets.

The LatticeECP4 FPGA family builds on the LatticeECP3 family by bringing premium features to mainstream users while maintaining industry-leading low power and low cost. The LatticeECP4 devices are ideal for developing mainstream platforms for a variety of applications such as remote wireless radio heads, distributed antenna systems, cellular basestations, Ethernet aggregation, switching, routing, industrial networking, video signal processing, video transmission and data center computing.

SerDes and hardened communication engines

The LatticeECP4 FPGAs contain up to 16 CEI-compliant 6-Gbps SerDes channels with embedded physical coding sub-layer (PCS) blocks in both low-cost wire-bonded and high-performance flip-chip packages, providing the option to deploy the LatticeECP4 FPGA in chip-to-chip as well as long-haul backplane applications. The configurable SerDes/ PCS can be seamlessly integrated with the hardened Communication Engines to economically build complete high-bandwidth sub-systems.

The Communication Engines offer up to 10X the power and cost reduction of similar implementations in FPGA fabrics. The LatticeECP4 Communication Engines portfolio includes solutions for PCI Express 2.1, multiple 10-Gbit Ethernet MAC and Tri-speed Ethernet MACs as well as Serial Rapid I/O (SRIO) 2.1. The combination of SerDes/ PCS and Communication Engines is ideal for completing complex serial protocol-based designs with lower cost, power and footprint while accelerating time to market.

DSP processing reduces multiplier count

The LatticeECP4 family features powerful digital signal processing (DSP) blocks with 18x18 multipliers, wide ALUs, adder-trees and carry chains for cascadability. Unique booster logic means each LatticeECP4 DSP block can be equal to four LatticeECP3 DSP blocks, enabling up to 4X the signal-processing capability of the previous generation LatticeECP3 devices. The flexible 18x18 multipliers can be split into 9x9 or combined into 36x36 to perfectly match customers' application requirements. Moreover, up to 576 multipliers can be cascaded together to build complex filters for wireless remote radio heads (RRH), MIMO-based RF antenna solutions and video processing applications.

The LatticeECP4 FPGAs are up to 50% faster than previous generation devices and feature 1066-Mbps DDR3 memory interfaces and 1.25-Gbps LVDS I/Os that are also capable of being provisioned as serial Gigabit Ethernet interfaces. The new LatticeECP4 family also has 66% more logic resources and 42% more embedded memory to empower design engineers to construct complete systems-on-chip in FPGAs.

Design support for LatticeECP4 FPGAs

Lattice provides intellectual property (IP) cores, development boards and design software for quick launch of design initiatives and rapid time-to-market. A range of intellectual property (IP) cores will include CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/ Gigabit Ethernet, PCI Express, SMPTE for serial connectivity, FIR filters, FFT, Reed-Solomon encoders/ decoders, CORDIC, CIC, NCO for DSP functions and several others for memory interfaces and connectivity.

Developers can begin designing with LatticeECP4 FPGAs now using the Lattice Diamond 1.4 beta design software. Lattice Diamond design software is the new flagship design environment for Lattice FPGA products and provides a complete set of powerful tools, efficient design flows and a user interface that enables designers to more quickly target low-power, cost-sensitive FPGA applications. In addition, Lattice Diamond software continues to provide features specifically developed for low-cost and low-power applications. These include a very accurate power calculator, pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions.

About the LatticeECP4 FPGA family

The LatticeECP4 FPGA family consists of six devices that offer standards-compliant multi-protocol 6G SerDes in low-cost wire-bond packages, DDR1/ 2/ 3 memory interfaces with speeds up to 1066Mbps, and cascadable DSP blocks that are ideal for high-performance RF, baseband and image signal processing. Toggling at 1.25Gbps, the LatticeECP4 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 10.6Mbits. Logic density varies from 30K LUTs to 250K LUTs with up to 512 user I/O. The LatticeECP4 FPGA family's high performance features include:
  • DSP blocks that allow up to 36x36 multiply and accumulate functions running at greater than 500MHz. The DSP slices also feature cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic. The DSP block offers booster logic, which allows 4X the bandwidth per DSP block relative to previous generation DSP architectures
  • 6-Gbps SerDes CEI-6G jitter compliance and the ability to mix and match multiple protocols on each SerDes quad. This includes PCI Express 2.1, CPRI, OBSAI, XAUI, Serial RapidIO 2.0, SGMII/ Gigabit Ethernet and 10-Gbit Ethernet.
  • The SerDes/PCS blocks have been designed specifically to enable the design of the low-latency-variation CPRI links that are found in wireless basestations with remote radio head connectivity.
  • Hardened Communication Engine blocks using hardened metal arrays featuring multiple 10GbE and Triple Speed MAC blocks, as well as PCI Express 2.1 and SRIO 2.1 blocks. These blocks are 10X more area- and power-efficient than traditional FPGA-based implementations.
  • Compliance to the SMPTE Serial Digital Interface standard, with the ability to support 3G, HD and SD video broadcast signals independently on each SerDes channel. The triple-rate support is performed without any oversampling technique, consuming the least possible amount of power.
  • 1.25-Gbps LVDS I/O, with clock data recovery blocks, allows interfacing to high-performance ADCs/ DACs and implementation of SGMII/GbE links. The ability to perform CDR functionality on general-purpose I/O greatly increases the number of serial I/O available to the designer, allowing smaller FPGAs to be used even when a large number of SerDes channels are needed, greatly reducing the cost of implementing serial Ethernet interface logic.


Select customers are already designing with LatticeECP4 FPGAs using the Lattice Diamond 1.4 beta design software. Device samples will be available in the first half of 2012 and high-volume production delivery is scheduled for the second half of 2012.

Go to the Lattice Semiconductor Corp. website for details.

E-mail Lattice Semiconductor Corp. for more information.

Read more about
Lattice Semiconductor Corp.

Keywords: FPGAs, field programmable gate arrays, FPGA design, SerDes, DSP, digital signal processing, digital signal processors, IP, intellectual property, cores, Lattice Semiconductor,
600/36253 11/28/2011 900 158
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