Page loading . . .

  
 Category: News: News Archive 2011: Saturday, May 25, 2013
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 (1623 Entries)
Numetrics to Provide Project Planning Tools to STMicroelectronics 

September 22, 2011 -- Numetrics Management Systems, Inc., a provider of resource and schedule estimation tools for semiconductor and embedded software projects, announced a multi-year agreement concluded recently with the Automotive Produ ... read more

Wind River and Leadcore Team to Develop and Test Android SOC 

September 22, 2011 -- Wind River and Leadcore Technology Co. Ltd. announced that the two companies have collaborated to develop a new Android system-on-chip (SOC) smartphone platform. Leadcore also implemented Wind River's testing softwar ... read more

IAR Systems Collaborates with Holt for MIL-STD-1553 Application Development Kits using ARM Cortex-M3 

September 22, 2011 -- IAR Systems AB has announced its collaboration with Holt Integrated Circuits, Inc. for its MIL-STD-1553 application development kit, HI-6130. Holt Integrated Circuits is a major supplier of ICs for avionics an ... read more

Giantec Semiconductor Moves to Cadence Technology 

September 20, 2011 -- Cadence Design Systems, Inc. today announced that Giantec Semiconductor, Inc. has adopted the Cadence Virtuoso unified custom/ analog (IC6.1) and unified digital flows for production of its mixed-signal chips. Giante ... read more

Altis Semiconductor Standardizes on Cadence MaskCompose Reticle and Wafer Synthesis Suite 

September 20, 2011 -- Cadence Design Systems, Inc. today announced that Altis Semiconductor, a European specialty foundry, standardized on the Cadence MaskCompose Reticle and Wafer Synthesis Suite to simplify and speed the path to ... read more

ASSET InterTech's New FPGA-Controlled Test (FCT) Inserts and Operates a Board-Tester-in-a-Chip 

September 20, 2011 -- With new tools for the ASSET InterTech, Inc. ScanWorks platform for embedded instruments, engineers can simply select instruments they need, set their parameters and insert them into a field programmable gate array ( ... read more

CST and Ageto MTT Announce Intensified Partnership 

September 20, 2011 -- Computer Simulation Technology (CST) and Ageto MTT announce an intensified partnership for local technical support in Sweden. Due to the increasing demand for CST's EM simulation tools, has invested in providing high ... read more

GOEPEL electronic Enables Graphical JTAG/ Boundary-Scan Project Development 
September 20, 2011 -- GOEPEL electronic GmbH has introduced a new graphical user interface (GUI) for the company's System Cascon JTAG/ boundary scan software platform.

Cascon Mission Assist enables completely graphical proje ... read more

Linear Technology Teams with AEi Systems to Offer WCCA and Spice Modeling 

September 20, 2011 -- Linear Technology Corp. has signed and implemented a multi-year cooperation agreement and program with AEi Systems, LLC to offer AEi Systems' and Linear Technology's customers and partner organizations (includ ... read more

Si2 Announces Agenda and Speakers for 16th Si2 Conference 

September 20, 2011 -- The Silicon Integration Initiative, Inc. (Si2) today announced that its 16th Si2 Conference will be held on October 20, 2011, at the Network Meeting Center-Techmart, Santa Clara, CA. The Conference will feature speak ... read more

Synopsys' DesignWare STAR Memory System Shipped in One Billion Chips 

September 20, 2011 -- Synopsys, Inc. today announced that its DesignWare STAR Memory System has shipped in one billion chips from semiconductor manufacturers worldwide, reinforcing its status as a trusted test and repair solution for embe ... read more

Synopsys Enhances Volume Diagnostics Solution to Accelerate Yield Ramp 

September 20, 2011 -- Synopsys, Inc. today announced new capabilities in TetraMAX ATPG and Yield Explorer that decrease the time, effort and cost of deploying a volume diagnostics flow and speed-up yield ramp.

When yiel ... read more

ChipWrights Releases Production-Ready, High-Definition 5-MPixel Camera Reference Design 

September 20, 2011 -- ChipWrights, Inc. has announced 5-MPixel 360° camera reference design with features that include: Aptina MT9P031 5-MPixel sensor, 80° fish-eye lens, Power-over-Ethernet, nuilt-in microphone, MicroSD card, aud ... read more

Sonics Unveils GigaHertz Network-on-Chip 

September 20, 2011 -- Sonics, Inc. today announced SonicsGN (SGN), the first GHz network-on-chip (NoC) for advanced, concurrent applications processing and system-level design. As the industry's highest-frequency NoC available today, SGN ... read more

Advanced IC Process-Characterization Tool Puts Reliability Data in Hands of Fabless Design Houses 

September 19, 2011 -- The Ridgetop Group, Inc. today introduced ProChek, an new system for rapid and inexpensive characterization of any semiconductor manufacturing process. With ProChek, any fabless IC supplier can independently collect ... read more

DFI Technical Group Releases Latest High-Speed Memory Controller and PHY Interface Specification 

September 19, 2011 -- The DDR PHY Interface (DFI) Technical Group today released the preliminary DFI 3.0 specification, the latest version of the industry specification that defines an interface protocol between DDR memory controllers and ... read more

Fujitsu Standardizes on Cadence DFM Technologies for 28-nm ASIC and Mixed-Signal Designs 

September 19, 2011 -- Cadence Design Systems, Inc. today announced that Fujitsu Semiconductor, Ltd. has adopted Cadence sign-off design-for-manufacturing (DFM) technologies for its 28-nanometer ASIC and system-on-chip (SOC) mixed-signal d ... read more

FuturePlus Systems Introduces DDR3 Protocol Analysis and Violation for BGA SDRAMs 

September 19, 2011 -- FuturePlus Systems Corp. is introducing new features for its DDR3 Detective. The DDR3 Detective monitors all DDR3 bus traffic continuously, while analyzing all behavior in real-time for several hundred different viol ... read more

Cadence Announces DFI 3.0-Compliant Design and Verification IP 

September 19, 2011 -- Cadence Design Systems, Inc. is now offering a comprehensive suite of solutions in support of the latest DDR PHY Interface (DFI) 3.0 specification (also announced today by the DFI Technical Group). Enabling the devel ... read more

IAR Systems Provides C99 Compliance to 8051 Software Tools 

September 19, 2011 -- IAR Systems AB has announced that its development toolsuite IAR Embedded Workbench for 8051 now complies with the ISO/IEC 9899:1999 standard, also known as C99. The company believes that the IAR C/C++ compiler is the ... read more




 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.600  2.921875