Page loading . . .

  
 Category: News: News Archive 2011: Tuesday, June 18, 2013
Sort Entries by    
Use the input form on the right to search on a word or phrase.  
Page(s): 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 (1623 Entries)
Energy Micro Adds 12 Devices to its Cortex-M3 Microcontroller Portfolio for Energy-Friendly Applications 

July 18, 2011 -- Energy Micro AS has announced availability of its EFM32 Gecko and Tiny Gecko product lines in a QFP64 package. The new 64-pin devices are particularly useful in the growing smart-metering market, in addition to energy-sen ... read more

Lattice Diamond 1.3 Design Software Delivers More-Robust Design Capabilities for Low-Power, Cost-Sensitive FPGA Applications 

July 18, 2011 -- Lattice Semiconductor Corp. today announced release 1.3 of its Lattice Diamond design software, the flagship design environment for Lattice FPGA products. Lattice Diamond 1.3 includes major new features such as clock-jitt ... read more

Renesas Electronics Achieves 4X Faster Performance with Synopsys' HAPS FPGA-Based Prototyping Solution 

July 18, 2011 -- Synopsys, Inc. today announced that Renesas Electronics Corp. adopted Synopsys' HAPS-64 FPGA-based prototyping systems for its prototyping environment for systems-on-chips (SOCs) and microcontrollers. By deploying the HA ... read more

Advanced Solid State Non-Volatile Memory Market to Grow 69% Annually Through 2015 

July 18, 2011 -- MarketResearch.com has announced the addition of the new report "Advanced Solid-State Memory Systems and Products: Emerging Non-volatile Memory Technologies, Industry Trends and Market Analysis," to its collection of comp ... read more

Lattice's New Mixed-Signal Design Software Simplifies Platform Management Design 

July 18, 2011 -- Lattice Semiconductor Corp. today announced release 6.1 of its PAC-Designer mixed-signal design software, with updated support for Lattice's Platform Manager, Power Manager II and ispClock devices. Users designing with Pl ... read more

IC Knowledge's Cost Analysis Shows Fully Depleted SOI Technology Most Cost-effective Approach at 22-nm Node 

July 14, 2011 -- Research firm IC Knowledge has completed a comprehensive cost analysis that determines fully depleted silicon-on-insulator (FD-SOI) wafers offer the global semiconductor industry the most cost-effective solution compared ... read more

Socle Licenses Cortex A9 MPCore for Next-Generation Platform Solutions 

July 14, 2011 -- Socle Technology Corp. today announced a new licensing agreement with ARM for the ARM Cortex A5, Cortex A8, and Cortex A9 MPCore multicore processors to expand its already existing ARM processor portfolio that includes AR ... read more

TSMC Qualifies Magma's QCP Extractor for 28-nm Designs 

July 13, 2011 -- Magma Design Automation, Inc. today announced that TSMC has included the QCP extractor in TSMC's quarterly EDA qualification report for 28-nm ICs. This qualification gives designers additional confidence in using Q ... read more

eMemory Offers eNVM IP in TSMC 80-nm High-Voltage Technology 

July 13, 2011 -- eMemory Technology, Inc.'s NeoBit one-time programmable memory, has been qualified in TSMC's 80-nm high-voltage (HV) technology, and has been successfully incorporated in high-definition (HD) display driver ICs fo ... read more

GlobalFoundries Fabs in New York and Dresden Achieve "Ready for Equipment" Milestone 

July 12, 2011 -- Just over one year after revealing plans for a major global capacity expansion, GlobalFoundries today announced its newly constructed cleanrooms in New York and Dresden are ready for the installation of 300-mm semiconduct ... read more

Micralyne and A.M. Fitzgerald & Associates Partner to Provide MEMS Design, Rapid Prototyping and Foundry Services 

July 12, 2011 -- Micralyne, Inc., a leading pure-play MEMS foundry serving high-performance biomedical, telecommunications and industrial markets, and A.M. Fitzgerald & Associates, LLC, a MEMS product development firm, today announ ... read more

GOEPEL electronic Supports picoChip in Testing Next-Generation "Small Cell" Baseband Chips  

July 12, 2011 -- GOEPEL electronic GmbH has developed special VarioTAP IPs for testing the new generation femtocell chips in cooperation with picoChip Designs, Ltd. The solution enables dynamic processor emulation tests (PET) for f ... read more

Cavium Networks Licenses Arteris FlexNoC Network on Chip Interconnect IP 

July 12, 2011 -- Arteris SA today announced that it has entered into an agreement with Cavium Networks, Inc. to provide Arteris' FlexNoC network-on-chip interconnect fabric IP.

"Arteris' NoC interconnect technolog ... read more

Berkeley Design Automation Expands Worldwide Sales and Support  

July 12, 2011 -- Berkeley Design Automation, Inc. today announced new agreements with leading EDA distributors in response to increased market demand for the Analog FastSpice Platform. Berkeley Design Automation has selected Neutronics So ... read more

Dream Chip Technologies Becomes Tensilica System-on-Chip Design Center Partner 

July 12, 2011 -- Tensilica, Inc. today announced that Dream Chip Technologies GmbH (DCT) has joined Tensilica's Xtensions partner network and become an authorized design center. As a Tensilica Xtensions partner, DCT will support cu ... read more

S2C Distributes Snowbush PCIe and SATA IP in China  

July 12, 2011 -- S2C, Inc. today announced its plans to distribute the Snowbush IP in China. The Gennum Snowbush IP Group offers one of the industry's most robust, widely-deployed and production-tested family of IP cores for today ... read more

Synopsys Announces Critical Milestone in 20-nm Design-Enablement Collaboration with Samsung Electronics 

July 11, 2011 -- Synopsys, Inc. today announced that its design-enablement collaboration with Samsung Electronics, Co., Ltd. has achieved a critical milestone with the successful tape-out of the first 20-nm test chip based on Samsu ... read more

Snowbush IP Group Launches New Multi-Standard PHY IP Platform on TSMC 28-nm Process 

July 12, 2011 -- Snowbush IP Group today announced the availability of its third generation of silicon-proven Multi-Standard (MS) PHY IP Platform on TSMC 28-nm technology. The new platform, which is capable of supporting a number ... read more

Synopsys Custom Design Solution Now Supported by GlobalFoundries 65-nm Process Technologies 

July 11, 2011 -- Synopsys, Inc. has collaborated with GlobalFoundries to jointly develop, validate, support and distribute interoperable process design kits (iPDKs) for GlobalFoundries' mainstream and advanced process technologies. ... read more

Synopsys Delivering Dual-Patterning-Compliant 20-nm IC Implementation Support 

July 11, 2011 -- Synopsys, Inc. today announced IC Compiler-Advanced Geometry, a new configuration of its leading IC Compiler physical design product. IC Compiler-Advanced Geometry targets design support for double-patterning technology ( ... read more




 Search for:
            Site       Current Category  
   Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
183.600  3.171875