| Mentor Graphics Works with Tezzaron and MOSIS on 3D-IC Prototyping Service |
June 6, 2011 -- Mentor Graphics Corp. is cooperating with Tezzaron Semiconductor and MOSIS to provide IC designers with a way to economically develop and manufacture 3D-IC prototypes on multi-project wafers (MPWs). The process enab ... read more |
| Mentor Graphics Mines Design and Test Data to Improve IC Yield and Failure Analysis |
June 6, 2011 -- Mentor Graphics Corp. has described a new use-model for net-based CAA and scan test diagnosis that minimizes physical failure analysis (PFA) cycle time and maximizes yield across multiple products. The approach, developed ... read more |
| Pulsic Introduces Integrated, Full-Chip Planning and Top-level Routing Solution for Custom IC Design |
June 1, 2011 -- Pulsic, Ltd. has introduced the Pulsic Planning Solution, a completely integrated full-chip solution built from the ground up for custom, analog and mixed-signal (AMS) ICs, the Pulsic Planning Solution automates planning a ... read more |
| Mentor Graphics Delivers Essential New Capabilities in TSMC AMS Reference Flow 2.0 |
June 6, 2011 -- Mentor Graphics Corp. has announced that a collection of tools has been validated for inclusion in TSMC Analog/Mixed-signal (AMS) Reference Flow 2.0, providing design enablement for TSMC 28-nm process technology. Ar ... read more |
| Synopsys and TSMC Collaborate to Deliver Custom Design Solution for 28nm TSMC AMS Reference Flow 2.0 |
June 6, 2011 -- Synopsys, Inc. has collaborated with TSMC to deliver Synopsys' custom design solution for TSMC's 28-nm Analog/Mixed-Signal (AMS) Reference Flow 2.0. Part of TSMC's comprehensive 28-nm design infrastructure, the flow ... read more |
| Sonics Announces Support for TSMC's Reference Flow 12 |
June 6, 2011 -- Sonics, Inc. today announced that it will support TSMC's Reference Flow 12 as part of the company's Open Innovation Platform (OIP) program targeting TSMC's most advanced 28-nm process technology. Over the last year, ... read more |
| BEEcube Announces miniBEE, a Full-Speed Mixed-Signal FPGA-Prototyping Platform Made Portable |
June 6, 2011 -- BEEcube, Inc. has announced that the miniBEE full-speed mixed-signal FPGA prototyping platform has been made "portable." miniBEE is similar to BEE4, but made smaller, offering application flexibility and customization as ... read more |
| Mentor Graphics Completes 28-nm Physical Design and Verification Flow for GlobalFoundries Technology |
June 6, 2011 -- Mentor Graphics Corp. has completed its 28-nm signoff-ready digital design flow for GlobalFoundries' technology. The sign-off-ready design flow is precisely tuned to address the unique challenges of designing and ma ... read more |
| Aldec, Cadence, Proximus Utilize OVP Fast Processor Models in System Design Solutions |
June 6, 2011 -- Imperas today announced that its Open Virtual Platforms (OVP) OVPsim simulator and OVP Fast Processor Models have been integrated with Aldec's Hardware Emulation Solutions (HES), Cadence Design System's Virtual Syst ... read more |
| Berkeley Design Automation and Tanner EDA Accelerate Circuit Verification for A/MS Designers |
June 6, 2011-- Tanner EDA and Berkeley Design Automation, Inc. are collaborating to integrate Tanner EDA's HiPer Silicon design suite with the Berkeley Design Automation Analog FasSpice Platform.
The seamless inte ... read more |
| Carbon Design Systems Performance, Power Analysis Tools Added to TSMC Reference Flow 12.0 |
June 6, 2011 -- Carbon Design Systems has announced that TSMC has added its SoC Designer Plus to TSMC Reference Flow 12.0 targeting TSMC's most advanced 28-nm process technology. These tools support performance and power analysis a ... read more |
| CAST Complements Popular 8051 Family with New 32-bit Processor Core Partnership |
June 6, 2011 -- Semiconductor intellectual property (IP) provider CAST, Inc. has reached an agreement with Beyond Semiconductor by which CAST will provide Beyond Semiconductor's BA22 processor core worldwide.
The ... read more |
| Ciranova Helix Provides 28-nm Support for TSMC AMS Reference Flow 2.0 |
June 6, 2011 -- Ciranova, Inc. has announced that its Ciranova Helix custom IC layout automation software has been selected for LDE-Aware Automatic Placement in TSMC Analog Mixed-Signal (AMS) Reference Flow 2.0, one of the critical ... read more |
| SpringSoft's Laker Custom Layout System Selected for TSMC 28-nm Reference Flows |
June 6, 2011 -- SpringSoft, Inc. today announced that its Laker Custom Layout Automation System has been selected by TSMC for the company's 28-nm Analog and Mixed-Signal (AMS) Reference Flow 2.0 and Reference Flow 12.0 for digital ... read more |
| Imperas and OVP Provide Free ARM Cortex-A8, Cortex-A9 and Cortex-M4 Fast Processor Models |
June 6, 2011 -- Imperas, Ltd., a member of the ARM Connected Community, has released its first models of the Cortex-A family of ARM processor cores. Models of the ARM Cortex-A series of cores, along with models of the Cortex-M series of c ... read more |
| S2C Announces Breakthrough FPGA-based Verification Module |
June 6, 2011 -- S2C, Inc. has developed the TAI Verification Module (patent pending), a prototype verification product that lets user designs in FPGA-based prototypes be verified with massive and fasttest benchs through a x4 PCIe Gen2 cha ... read more |
| MathWorks HDL Tools Add Xilinx FPGA Hardware Verification |
June 2, 2011 -- MathWorks, Inc. today announced the availability of EDA Simulator Link 3.3 with new FPGA-in-the-loop (FIL) capabilities for Xilinx FPGA development boards. FIL enables engineers to verify their designs at hardware speeds w ... read more |
| IC Manage Announces IP Central to Maximize IP Reuse |
June 2, 2011 -- IC Manage, Inc. today announced that the IC Manage Global Design Platform (GDP) has been extended to include IP Central, an open platform for maximizing IP reuse. Design and verification teams can use IP Central to rapidly ... read more |
| Lorentz Solution Collaborates with Cadence to Enhance RFIC Design Solutions |
June 1, 2011 -- Lorentz Solution, Inc. today announced a joint marketing agreement (JMA) with Cadence Design Systems, Inc. aimed at providing more tightly integrated solutions for RFIC and high-speed analog designers.
... read more |
| Lorentz Solution's PeakView Supports TSMC RF Reference Design Kit 3.0 |
June 1, 2011 -- Lorentz Solution, Inc. today announced that PeakView EM solution for Chemical and Mechanical Polishing (CMP) has been included in TSMC's 65-nm RF Reference Design Kit RDK 3.0. The PeakView CMP-Enabled EM solution pr ... read more |
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