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 Category: News: News Archive 2012: Monday, May 20, 2013
Lattice Announces New Power-Management Architecture  
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May 7, 2012 -- Lattice Semiconductor Corp. today announced a scalable, in-system up-gradable, star topology power-management architecture that can be used across a wide range of circuit boards requiring more than 12 power supply rails. Lattice has simultaneously made available two new application notes for its aPlatform Manager devices that will enable designers to quickly adopt the new architecture.

Power-management functions include supply sequencing, monitoring, hot-swap control, reset and other supervisory signal generation. The complexity of power-management functions grows significantly when the number of circuit board power supplies increases. The solution often demands the use of multiple power-management devices. As a result, designers typically are forced to partition the overall power-management task and implement it using distributed algorithms in multiple devices; a costly and time consuming approach. The inadequacies of this approach become apparent only during the board-debug stage, forcing board re-spin and costly project delays. The integrated power-management approach made possible by the Platform Manager devices, on the other hand, reduces cost and increases board reliability.

About the Platform Manager family

The Platform Manager product family consists of two devices: the LPTM10-1247 and LPTM10-12107. The LPTM10-1247 device can monitor 12 power supply rails and supports 47 combined digital inputs and digital outputs, while the LPTM10-12107 monitors up to 12 power supply rails and supports 107 combined digital inputs and digital outputs. Functionally, these devices include both a power-management section and a digital-board-management section. The power-management section consists of a programmable threshold, precision differential-input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies. The digital board management section consists of a 640-LUT FPGA and programmable logic interface I/O.

The application notes describe unrestricted access to power supply status indicators and the ability to control all board management functions. Designers are easily able to modify their algorithm to meet unforeseen power management requirements and minimize the need for a board re-spin.

The two new Platform Manager application notes are:

  • AN6089: Scalable Centralized Power Management with Field Upgrade Support
    • Describes how the Platform Manager device can be used as a centralized controller to implement flexible sequencing and precision monitoring of up to 36 power supply rails on a circuit board.
    • Discusses the use of a star topology and fast serial interface to provide a seamless, scalable solution to manage up to 36 power supply rails using additional Lattice Power Manager II devices.
  • AN6088: Fail-Safe Sequencing During Field Upgrades with Platform Manager
    • Describes how to enable field updates to the power management algorithm with a fail-safe sequencing backup that restores board operation if the field update procedure is interrupted.

Designs for the Power Manager II and Platform Manager devices are implemented using Lattice PAC-Designer and Lattice Diamond design software tools that are available for download free of charge from the Lattice website.



Go to the Lattice Semiconductor Corp. website for details.

E-mail Lattice Semiconductor Corp. for more information.

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Lattice Semiconductor Corp.
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Keywords: FPGAs, field programmable gate arrays, FPGA design, power analysis, power optimization, power management, Lattice Semiconductor
601/38390 5/7/2012 420 69


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