May 22, 2012 -- Cortus SA has announced the release of the latest member of its processor family: the energy-efficient APS3R. The APS3R builds on experience with the earlier APS3 core but delivers improved computational performance. For more demanding embedded applications a dual-core configuration is possible.
The Cortus APS3R is a 32-bit processor designed specifically for low-power embedded systems featuring a 32-bit modern RISC architecture with sixteen 32-bit registers and a 5- to 7-stage pipeline. It is the second member of the Cortus microcontroller IP core family to be released in 2012 complementing the single-precision floating-point FPS6 core.
"Our first processor core, the APS3, has been the smallest available native 32-bit IP core since its release in early 2006," says Michael Chapman, CEO and President of Cortus, "With the new APS3R we have found new ways to raise computational performance while keeping power consumption and silicon area small. APS3R extends Cortus’ advantage in terms of DMIPS/mW and DMIPS/mm² over alternative cores."
The CPU's dynamic power is 11.6µW/MHz with a standard 90-nm process and 16.8µW/MHz for 130nm (both UMC). The APS3R delivers 1.21 CoreMarks/MHz and 2.29DMIPS/MHz computational performance.
The APS3R CPU core can be as small as 8,700 gates which is a size comparable to most 8-bit cores. APS3R is a native 32-bit core, optimized for use with C or C++, resulting in a software-development process that is more straightforward than that for 8- or 16-bit cores. With more computation per clock cycle than with an 8-bit core, far fewer cycles are needed and, therefore, considerably less power is required. With superior code density, code memory is also smaller than with 8- or 16-bit cores thus reducing the silicon footprint of a subsystem.
The APS3R has been developed for applications requiring good computational performance but very low power. It is well-suited to applications such as wireless communication, sensing, smart cards, SIM cards, touchscreen controllers and systems using energy harvesting.
For more computationally demanding applications, an optional parallel hardware multiplier can improve the core performance to 1.92 CoreMarks/MHz. Further improvements are possible with a dual-core APS3R configuration.
As a member of the Cortus family of processors, APS3R interfaces to all of Cortus' peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. It also shares the simple vectored interrupt structure which ensures rapid, real-time interrupt response, with low software overhead. Bridges to and from AHB-Lite and to APB ensure easy interfacing to other IP.
The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customized and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium µC/OS and µCLinux.
Go to the Cortus SA website to find additional information.