| Aldec at DAC 2012 with 10 Face-to-Face Sessions | | |
May 24, 2012 -- Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions, will bring its top engineers to meet one-on-one with attendees at the annual Design Automation Conference (DAC), June 3-7, 2012 at the Moscone Center in San Francisco, Calif. Aldec offers convenient pre-registration for technical sessions on its website.
Registrations confirmed to date indicate the top trending Aldec sessions at DAC are:
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Simulation on the Cloud: Unlimited Possibilities - Aldec has enabled running RTL and timing simulation on the secured cloud, providing access to a virtually unlimited number of high-performance servers.
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UVM in Aldec Tools: Verification and Debugging - Aldec's support of the latest UVM library, graphical debugging features to help designers find and fix issues more efficiently, and exciting future enhancements coming later this year.
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High-Level VHDL Verification Doing Well with Help of New OS-VVM Community - Aldec, an early OS-VVM supporter, is hosting an open OS-VVM User Group Meeting on Monday, June 4, 2012 at 2:00pm in Booth #2126.
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Emulation Achieve 10+ MHz emulation of 100 million ASIC Gates with true RTL debugging; hardware and software design teams can also now use virtual platforms with transaction level emulation.
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Other popular Aldec sessions include:
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Requirements-based FPGA Testing Method for DO-254.
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Early Validation of Custom IP for Zynq-based Designs.
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Interoperable IP Encryption (P1735): Safe and Smooth Multi-vendor Encryption Flow.
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A Highly Productive, Integrated Analog Mixed-Signal (A/MS) Solution from Tanner EDA.
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Ask Aldec (Questions, Updates, Roadmaps).
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Go to the Aldec, Inc. website for details.
| E-mail Aldec, Inc. for more information.
Read more about
Aldec, Inc.
on SOCcentral.com |
| Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, Aldec,
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