May 24, 2012 -- Uniquify, Inc. today launched ideas2silicon, a new and comprehensive design services platform that spans chip specification and design through volume delivery of packaged and tested parts. ideas2silicon offers faster turnaround, lower costs and a transparent business model that gives project teams complete visibility into the cost structure.

"The traditional turnkey model is not working and we're doing something about it,! says Josh Lee, CEO and founder of Uniquify. !Projects teams have been frustrated with the classic model, as it effectively locks them into an expensive business relationship that is hard to change. Perseus, a proven proprietary design framework for fast, repeatable and consistent turnaround on complex designs, forms the foundation of ideas2silicon. It provides a disciplined methodology for managing the design and closure of complex system-on-chip (SOC) and Super SOC (SSOC) designs with multiple processors, special-purpose processing engines, on-chip networks, memories and different peripheral and I/O functions."

More about ideas2silicon design services platform

ideas2silicon delivers predictable and efficient execution of the most complex ASIC, SOC and SSoC designs. A key component is an automated capability for rapidly selecting, qualifying and integrating IP blocks that form the backbone of a new design.

Availability of this IP affords project teams earlier testing and verification of their own differentiating design blocks and IP. Services range from specification and architectural design, field programmable gate array (FPGA) prototyping, register transfer level (RTL) design and verification through complete physical design and verification.

Uniquify’s highly qualified design team has expertise in advanced 65-, 40- and 28-nanometer process technologies from foundries including TSMC, Samsung, GlobalFoundries and SMIC. These design experts have experience meeting the stringent performance, low power, OCV-aware, IP integration and verification, design-for-manufacturing and requirements of a project team's most challenging SOC designs.

Uniquify partners with EDA suppliers, including Cadence, Mentor and Synopsys, for the automation software needed to support these complex designs within Perseus.

For SOCs with an IP content of 50% to 60% or more, Uniquify has developed a portfolio of patented, high-performance DDR memory subsystems that can be applied for rapid implementation to address the need for tested and pre-qualified IP.

Uniquify recognizes that delivering IP functionality alone is not sufficient, but must be "variation aware" as well. It developed variation-aware, high-performance and silicon-proven Self-Calibrating Logic and Dynamic Self-Calibrating Logic (DSCL) IP for DDR memory subsystems to solve both static and dynamic variation problems during system operation. This patented technology includes controllers, PHY and I/O for use on a variety of applications.