May 29, 2012 -- Calypto Design Systems, Inc. today announced Catapult Low-Power (LP), a production-quality, high-level synthesis (HLS) tool that adds power as an optimization goal. By leveraging Calypto's existing power-analysis and optimization technology, Catapult LP provides a closed-loop optimization across power, performance and area (PPA) to address the challenges of power-aware design.

Catapult LP takes advantage of Calypto's unique PowerPro technology by embedding it "under the hood" of Catapult to seamlessly produce the lowest-power RTL and optimize designs at the architecture level where 80% of power decisions are made. Catapult LP enables designers to explore different hardware architectures and measure the power, performance and area of each solution. The net result is an ability to perform architectural refinement from an abstract C++ or SystemC model and deliver closed-loop PPA optimization from high-level synthesis.

Catapult LP goes beyond the architecture level by leveraging Calypto's patented sequential analysis technology to deliver automatic fine-grain clock gating. This two-prong approach of optimizing the architecture followed by maximizing clock-gating efficiency at the register level promises the greatest power savings.

In addition to Catapult LP, Calypto is also announcing PowerPro Power Analyzer (PA) 6.0, which adds production-ready power analysis. PowerPro PA provides RTL power estimation within 15% of gate level in a fraction of the time. With PowerPro PA designers can quickly estimate block-level power such as dynamic, leakage, peak, average and generate toggle-activity reports. Combining PowerPro PA with Calypto's PowerPro optimization platform creates a comprehensive, low-power flow across the entire SOC platform.

Catapult LP and PowerPro PA will be demonstrated at the Design Automation Conference (DAC), June 3-6, Moscone Convention Center, Booth #1226.