June 18, 2012 -- Xilinx, Inc. today announced its expanded forward error correction (FEC) intellectual property (IP) offering. The offering includes GFEC, EFEC and high gain FEC (xFEC) solutions used to obtain error control in signal transmission and extend the distance of a transmission that reduces the number of regenerators (hops) along the route, which reduces OpEx and CapEx costs for network operators.
Xilinx designed these FEC IP cores with a common interface to accelerate product development, minimize system-level integration time, maximize design reuse and reduce time-to-market. The ultra compact, high-performance FEC cores — which include GFEC IP cores for 2.5G, 10G, 40G, 100G applications, legacy 10G EFECs and a Xilinx Extended FEC (xFEC) IP core for 100G applications — were optimized specifically for Xilinx FPGAs to occupy less silicon real estate than non-Xilinx IP cores, making them the smallest FEC cores available. Xilinx is also working to add 400G GFEC for leading-edge applications to be available Q2 2013. Combined with partial reconfiguration, these IP cores optimized for Xilinx FPGAs enable designers to integrate multiple FEC standards on multiple interfaces, while reducing product costs, power consumption and maximize network interoperability.
About forward error correction
The use of forward error correction maintains error control between the source (transmitter) sending redundant data signals and the destination (receiver) that recognizes only the portion of the data containing no apparent errors. Used in all OTN systems, FEC provides coding gain that lets users transmit a signal over a greater distance by correcting errors that can happen as the signal-to-noise ratio decreases with distance, yet still achieve the same error rate at the far end receiver.
Different FEC schemes provide different levels of coding gain. The higher the coding gain, the greater the distance an optical signal can be transmitted. As an example, the Xilinx 100G Extended FEC (xFEC) provides an industry-leading 9.4-dB NECG at 6.7%t OH that increases 100G transmission distances and reduces 100G transmission power.
The coding gain provided by FEC is used to do multiple functions including increasing the maximum span length and/or the number of spans that results in extending system reach. This is also useful for increasing the number of dense wavelength division multiplexing (DWDM) channels in a system which is typically limited by the output power of the amplifiers being used. This coding gain also decreases the power per channel and increases the number of channels or relaxes the component parameters (e.g., launched power, eye mask, extinction ratio, noise figures, filter isolation) for a given link and lowers the component costs.
The Xilinx OTU1, 2, 3 and 4 (2.5G, 10G, 40G and 100G) GFEC IP cores are compliant to the ITU G.709 standard and are available today. The 100G high gain xFEC will be available in December 2012. Xilinx will also be adding other EFEC standard implementations based on customer demand.
Xilinx FEC IP cores are cost competitive and only require a single project license with no recurring royalty fee. For full access to all core functionality in simulation and in hardware, a license for a core must be purchased.
Go to the Xilinx, Inc. website to find additional information.