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 Category: News: News Archive 2012: Saturday, May 25, 2013
Aldec and Agilent Technologies Bridge the Gap Between ESL and RTL by Linking Simulation Environments  
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July 10, 2012 -- Aldec, Inc. has worked with Agilent Technologies to deliver a new co-simulation interface between the latest version of Riviera-PRO, Aldec's popular design simulation and verification platform used by FPGA, ASIC, and SOC development teams, and SystemVue, Agilent's ESL-design and signal-processing environment used by system architects and algorithm developers in physical layer designs of wireless, RF and DSP applications. The new solution enables users to efficiently integrate algorithm and system-level designs with hardware implementations.

"Agilent system-level-design products are now integrated into the hardware-design flow, which enables system engineers to troubleshoot Verilog and VHDL hardware implementations, while still maintaining a higher-level view of physical-layer (PHY) system performance," said Daren McClearnon, Agilent's SystemVue Product Marketing Manager. "Our respective R&D teams worked closely together to create a high-performance, yet cost-efficient, co-simulation interface that unites baseband, RF, simulations, and measurements in single, system-level cockpit."

The new co-simulation interface requires only one instance of Riviera-PRO (regardless of the number of HDL blocks on a SystemVue diagram), supports a range of data types, and provides extensive cross-domain debugging capabilities. This tight, bi-directional integration reduces development time and effort by enabling continuous test and system-level verification throughout the development process. "The Agilent SystemVue co-simulation interface brings several exciting new features to hardware design verification engineers, our traditional customers," said Dmitry Melnik, Riviera-PRO Product Manager. !It enables the link to a powerful RF System simulator, RF EDA tools and models, trusted references for emerging communications standards, and even test and measurement equipment if necessary. Now engineers can re-use SystemVue components in hardware simulations while respective HDL blocks are being coded, or use SystemVue as a testbench to verify HDL implementation.!

Availability

To access the interface, valid licenses for the latest versions of both Riviera-PRO and SystemVue are required; current license holders are encouraged to upgrade.

For the latest on Aldec's Riviera-PRO release version 2012.06, including free, 30-day evaluation downloads, tutorials, and more, please visit Riviera-PRO.

For more on Agilent's SystemVue 2012.06, including free, 30-day evaluation downloads, videos, and more, visit SystemVue.



Go to the Aldec, Inc. website to find additional information.

E-mail Aldec, Inc. for more information.

Read more about
Aldec, Inc.
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Agilent EEsof EDA
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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, electronic system level design, electronic system-level design, ESL, simulation, simulators, Aldec, Riviera-PRO, Agilent EEsof EDA, SystemVue,
601/38820 7/10/2012 425 71


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