| Flexible and Novel Partitioning Strategy for Hierarchical Design by Freescale Semiconductor, Inc. in EE Times EDA Designline |
December 27, 2012 -- In the competitive semiconductor world, most of the organization tries to put many applications and features into a single design. To come up with the demanding multi-featured design, SOCs are getting complex and a need to p ... read more |
| Multicore's Place in the Real-Time World by Micrium, Inc. in Electronic Products Magazine |
December 26, 2012 -- Multicore CPU architectures are a little like hybrid vehicles: Once seen as anomalies, both are now encountered on a regular basis and are widely accepted as possible solutions to challenging problems. Also, much as hybrid d ... read more |
| Customizing SRAM Content to Obtain Truly Differentiated Products by eSilicon Corp. in Chip Estimate Corp. |
December 25, 2012 -- As the three C's comprising convergence of computers, communication and content (multimedia) continue, they increase memory content in SOCs. SOCs aggregate functionality with multiple CPUs, which must run at stringent power ... read more |
| Seismic Shifts Await EDA in a More-than-Moore World by Atrenta, Inc. in Electronic Design Magazine |
December 20, 2012 -- The EDA and semiconductor intellectual property (IP) markets demonstrated good growth and achieved some good exits in 2012. However, one development stands as the most significant, dire, and opportunistic factor that will be ... read more |
| Hybrid Execution and Software-Driven Verification Will Emerge in 2013 by Cadence Design Systems, Inc. in Electronic Design Magazine |
December 19, 2012 -- Last year, I predicted that two things would happen in 2012. First, I suggested that the hybrid, combined use of TLM simulation and the various ways to execute RTL (including hardware-assisted verification) would find further adopt ... read more |
| Companies Ramp Up to Move from 20nm to the Next Node in 2013 by Mentor Graphics Corp. in Electronic Design Magazine |
December 18, 2012 -- Well, 2012 has come to a close. It looks like all the Mayan "end is nigh" forecasts were good movie hype, but we're all still here. In fact, fabless companies, foundries, and EDA suppliers have made real progress in preparin ... read more |
| Reduce Power in Chip Designs with Sequential Clock Gating by Calypto Design Systems, Inc. in Electronic Design Magazine |
December 17, 2012 -- Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions in the RTL, which the s ... read more |
| Formal Methods for Power-Aware Verification by Jasper Design Automation in EE Times EDA Designline |
December 17, 2012 -- The imperative for reducing power consumption now pervades application spaces ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Conseq ... read more |
| Dither Can Boost Sampled Data System Performance by at Least 10dB by e2v in Electronic Design Magazine |
December 13, 2012 -- Sample rates for analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) continue to evolve, now reaching 5GSps at 10-bit resolutions and 1.5GSps at 12 bits. These devices have traditionally fallen within ... read more |
| Enabling 3D-IC design by Synopsys, Inc. in Tech Design Forum |
December 12, 2012 -- As planar integration becomes more complex, integrating IC functions in three dimensions becomes more attractive. Although the tool, packaging and semiconductor industries have some way to go before it is possible to place a ... read more |
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