|Publication: Design & Reuse|
Contributor: Synopsys, Inc.
March 1, 2012 -- This article presents some key concepts necessary to design and build high-quality, mixed-signal IP in 28-nm or smaller geometries. The article addresses specific design, layout, and verification techniques to address challenges posed in 28-nm technology nodes. Specifically, the article focuses on three main areas where 28-nm technologies pose some unique challenges, low-power design, restricted design rules, and design-for-yield. Several design examples are presented, highlighting key techniques employed in the Synopsys DesignWare mixed-signal intellectual property portfolio.
By Brent Beacham, Paul Hua, Cameron Lacy, Michael Lynch, and Dino Toffolon. (All the authors are with Synopsys, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
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|Keywords: ASICs, ASIC design, IP, intellectual property, cores, mixed signal design, mixed-signal design, EDA, EDA tools, electronic design automation, Synopsys, Design & Reuse|
|602/37991 3/1/2012 1163 110|