Page loading . . .

 Category: Magazine & Journal Articles Online: Article Archive 2012: Saturday, November 28, 2015
Design Calculations for Robust I2C Communications  
Publication: EE Times Memory Designline
Contributor: Microchip Technology, Inc.
 Printer friendly
 E-Mail Item URL

April 23, 2012 -- For many systems that require reliable non-volatile storage, EEPROM is the memory technology of choice. EEPROM features a robust architecture, with multiple suppliers and many years of refinement. EEPROM devices are available in a variety of industry-standard serial buses, including I2C, SPI, Microwire, and the UNI/O bus. Due to its widespread hardware support in microcontrollers and other chipsets, and the fact that its easy signaling enables efficient implementation with minimal silicon, the I2C bus comprises approximately 70% of the non-volatile memory market.

The I2C bus topology relies on correctly sized pull-up resistors for reliable, robust communications, however. Selecting the wrong resistor values can not only result in wasted power, but can also lead to erroneous bus conditions and transmission errors caused by noise or changes in temperature, operating voltages, and by manufacturing variations between devices.


By Chris Parris and Jonathan Dillon. (Parris and Dillon are senior applications engineers at Microchip Technology, Inc.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times Memory Designline website.

Read more about
Microchip Technology, Inc.

Keywords: PCB design, embedded system design, embedded systems, I2C, computer system design, general-purpose computers, special-purpose computers, Microchip Technology, EE Times Memory Designline
602/38335 4/23/2012 620 120
Designer's Mall

 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
and receive news, article, whitepaper, and product updates bi-weekly.


Verification Contortions

Dr. Lauro Rizzatti
Verification Consultant
Rizzatti, LLC

Real Talk

Drilling Down on the Internet of Things

Ramesh Dewangan
VP Product Strategy
Real Intent, Inc.

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
DSP Design
Analog Design
Digital Design
Mixed-Signal Design
RF Design
EDA Tool Development

IC Packaging
PCB Design
RTOS Development
RTL Design
SystemC Design
SystemVerilog Design
Verilog Design
VHDL Design

Post a Job
Only $100 for 30 days

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Design Center
Tutorials, Whitepapers & App Notes
Archived Webcasts


Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.602  0.265625