April 30, 2012 -- The intent of this design article is to provide a comprehensive tutorial on both the value of and the "how to" in using a hierarchical low-power design methodology. The article first shows how to express power intent top-down in a hierarchical design, which allows the designer to set rules abstractly without worrying about the details of all the power domain crossings lower in the design hierarchy.
The article then describes the concept of macro modeling to capture power intent for IP blocks. Next, it illustrates a bottom-up hierarchical approach that enables the designer to integrate the same block in multiple situations that require different uses of the block's internal power intent capabilities. Finally, the article describes how to use virtual ports and virtual power domains to simplify specification of rules for design objects that will later appear lower in the hierarchy, as the design implementation is refined.
Although the Common Power Format (CPF) is used as the main format to illustrate these capabilities, not all of these hierarchical capabilities are truly unique to CPF. The hierarchy support currently provided in the IEEE 1801 standard, Unified Power Format (UPF) 2.0, is also covered. The article concludes by reviewing recent developments toward methodology convergence between the Silicon Integration Initiative Low Power Coalition, which is responsible for CPF, and IEEE P1801.
By Luke Lang. (Lang is an Engineering Director in the Cadence Design Systems, Inc. Low-Power Product Engineering group focusing on low-power architecture, methodology, and deployment.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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