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 Category: Magazine & Journal Articles Online: Article Archive 2012: Saturday, May 18, 2013
Power: A Significant Challenge in EDA Design  
Publication: EDN Magazine
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May 24, 2012 -- Power is the rate at which energy is consumed; not a hot topic 10 years ago but a primary design consideration today. A system's consumption of energy creates heat, drains batteries, strains power-delivery networks, and increases costs. The rise in mobile computing initially drove the desire to reduce energy consumption, but the effects of energy consumption are now far-reaching and may cause some of the largest structural changes in the industry. This issue is important for server farms, the cloud, automobiles, chips, and ubiquitous sensor networks relying on harvested energy.

The reason for the sudden change is that physics was helping with process technologies down to 90nm. With each increasingly smaller node, however, voltages decreased, creating a corresponding drop in power. In general, power budgets remained fixed even as developers integrated additional capabilities. With smaller geometries, voltage scaling is more difficult and is failing to keep up. As voltages approach the threshold voltage, switching times increase. To compensate, designers lowered threshold voltages, but doing so caused a significant increase in leakage and switching currents.

Every stage in the design flow, from software architecture to device physics, affects power consumption. Although each team can locally optimize power consumption, no single group can create a low-power design. Conversely, any one group can destroy it. This situation is creating a new need for cooperation and cross-discipline tooling. Power issues do not stop on chip. They spread to interconnect topologies, board and system design, power controllers, and so on. Current EDA tools do not build in the concept of power, meaning that designers are adopting retrofit approaches rather than rebuilding from the ground up.

 

By Brian Bailey, EDN Contributing Technical Editor.


This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EDN Magazine website.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, power analysis, power optimization, low power design, low-power design, EDN Magazine,
602/38554 5/24/2012 543 70


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