May 22, 2012 -- Since the dawn of the semiconductor industry, manufacturers have successfully ramped silicon yield at each process node, using yield-management systems (YMS) and physical failure analysis (PFA). When the majority of the industry shifted from being integrated devices manufacturers (IDMs) to fabless semiconductor companies, a new yield-improvement strategy was adopted: Blame the Foundry. The logic is that all designs that meet design rule checks (DRCs) should be equally manufacturable. Poor yield is, therefore, the fault of the foundry.
Blaming the fab no longer works. The ability to effectively separate design- and process-oriented yield issues, and to identify the most effective corrective action, is now an important part of the yield-analysis process. Resolving these design-induced systematic defects is one of the few ways that fabless semiconductor companies can directly improve yield.
Enter a new DFM-aware yield-analysis flow that combines production test failure diagnosis with DFM analysis. It enables engineers to identify and understand systematic yield loss, and to determine whether the systematic yield loss is correlated to DFM violations. While the concept of combining design and silicon test analysis has been around for years, the problem has only recently touched a large portion of the industry and so driven the creation of practical solutions.
By Geir Eide. (Eide is a Product Marketing Manager in the Silicon Test Solutions group at Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Tech Design Forum website.
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