June 18, 2012 -- Part 2 of this three-part series investigates hardware and SPI protocol changes that increase serial NOR flash memory throughput. Part 1 reviewed system-level and memory-device strategies that allow higher read-throughput for economical NOR flash memory.
Significant focus has also been placed on minimizing the protocol overhead on the SPI bus. One advantage that parallel (NOR) buses have is the ability to instantly identify the transaction that needs to be performed. Serial devices incur additional latency because the command to perform and the target address is presented in a serial (or "semi-serial") fashion. This serial process requires several clock cycles just to fully describe the operation to perform.
In the multi-IO versions of the SPI protocol, the target address and sometimes the command, is presented in a multi-bit-wide manner to minimize the number of clock cycles required to initiate an operation. Other strategies to minimize command, address, and data transfer overhead are described.
By Cliff Zitlaw. (Zitlaw is with Spansion, Inc.)
This brief introduction has been excerpted from the original copyrighted article.