June 25, 2012 -- The AMBA 4 specification for the connection and management of functional blocks in a system-on-chip (SOC) now features Advanced eXtensible Interface (AXI) coherency extensions (ACE) in support of multicore computing. The ACE specification enables system-level cache coherency across clusters of multicore processors.

When planning the functional verification of such a system, these coherency extensions bring their own complex challenges, such as system-level cache-coherency validation and cache-state-transition validation. At any given time, it's important to verify that the ACE interconnect can maintain cache coherency across the different ACE masters in the system. Cache-state-transition validation involves verifying the ability of the ACE interconnect to handle all cache line state transitions in ACE masters in the system. This requires a high degree of configurability and responsiveness in the stimulus-generation infrastructure, as well as a robust checking mechanism for validating the system-level cache coherency.

This article describes how the Universal Verification Methodology (UVM) configuration mechanism can be leveraged to optimize configurability of the sequences.

By Peer Mohammed, Romondy Luo, Ray Varghese, Parag Goel, Amit Sharma, and Satyapriya Acharya. (Mohammed is a senior design engineer at MindSpeed Technologies; Luo is a CAE Manager at Synopsys, Inc.; Varghese is a senior R&D Engineer at Synopsys; Goel is a senior CAE at Synopsys; Sharma is a senior CAE manager at Synopsys; and Acharya is a senior CAE at Synopsys.)