|Publication: EE Times Embedded|
Contributor: Freescale Semiconductor, Inc.
July 16, 2012 -- In SOCs (systems-on-chip) used for automotive applications, embedded flash memories take up almost 50% of the die area; the rest of the area is used for SoG (sea of gates). To deal with signal routing, memories are totally blocked in all layers and power routing is partially blocked because the memories are sensitive to noise.
Placing such blocks is a knotty task because to avoid die wastage it must be accomplished with minimum routing channels. Currently there is no tool available to do automated macro placement intelligently considering data flow diagram (DFD), timing, and routability. As a result, manual placement of hard macros is a must to come up with a routing friendly floor plan. This process, being iterative, eats up huge cycle time and affects the die-size estimate.
In this article, we propose a SMP (smart macro placement) algorithm for reducing die size, improving IR drop, and reducing cycle time. The proposed SMP algorithm covers the following key points:
- In-place flipping of macros, based on internal cell blockages to decide the best orientation.
- Checks all possible orientations that may be missed manually.
- Outputs the best orientations in one go, thus saving on iterations and cycle time.
By Gurinder Singh Baghria, Sonal Ahuja, Rishi Bhooshan, and Sumit Varshney. (The authors are all with Freescale Semiconductor, India Pvt, Ltd.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times Embedded website.
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Freescale Semiconductor, Inc.
|Keywords: ASICs, ASIC design, mixed signal design, mixed-signal design, EDA, EDA tools, electronic design automation, Freescale Semiconductor, EE Times Embedded, system-on-chip, SoC, |
|602/38868 7/16/2012 580 99|