Page loading . . .

  
 Category: Magazine & Journal Articles Online: Article Archive 2012: Wednesday, May 22, 2013
Using Code-Coverage Analysis to Verify 2D Graphic Engines in Automotive Apps  
Publication: EE Times Automotive Designline
Contributor: Fujitsu Microelectronics Europe GmbH
 Printer friendly
 E-Mail Item URL

July 20, 2012 -- High-resolution graphics displays are becoming a key part of automotive manufacturers' strategies to simultaneously differentiate from their competitors, reduce production cost, and increase customer satisfaction. Our group at Fujitsu develops IP blocks and SOCs to help developers realize these advantages.

One of our IP blocks is called Iris, a 2D-graphics engine. This IP is composed of many reusable sub-components, which can be easily rearranged to create new derivatives of Iris that are then integrated into a range of products. All of these sub-components, of course, need to be verified in addition to the final product. For this purpose, we employ a metric-driven verification flow.

By Florian Mueller. (Mueller is a design engineer at Fujitsu Semiconductor Europe (FSEU).)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Automotive Designline website.

Read more about
Fujitsu Microelectronics Europe GmbH
on SOCcentral.com

Keywords: ASICs, ASIC design, IP, intellectual property, cores, graphics processors, graphics processing units, GPUs, EE Times Automotive Designline, Fujitsu Microelectronics
602/38872 7/20/2012 804 107


Designer's Mall
0.15625



 Search for:
            Site       Current Category  
   Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
184.602  0.234375